JAJSD41E April 2017 – April 2018 TUSB544
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VCC | P | 3.3 V Power Supply |
2 | UEQ1/A1 | 4 Level I | This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. Up to 9.4 dB of EQ available. In I2C mode, this pin will also set TUSB544 I2C address. Refer to Table 10. |
3 | CFG0 | 4 Level I | CFG0. This pin along with CFG1 will select VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 8 for VOD linearity range and DC gain options. |
4 | CFG1 | 4 Level I | CFG1. This pin along with CFG0 will set VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 8 for VOD linearity range and DC gain options. |
5 | SWAP | 2 Level I | This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data path inputs.
0 – Do not swap channel directions and EQ settings (Default) 1. – Swap channel directions and EQ settings. |
6 | VCC | P | 3.3V Power Supply |
7 | SLP_S0# | 2 Level I | This pin when asserted low will disable Receiver Detect functionality. While this pin is low and TUSB544 is in U2/U3, TUSB544 will disable LOS and LFPS detection circuitry and RX termination for both channels will remain enabled. If this pin is low and TUSB544 is in Disconnect state, the RX detect functionality will be disabled and RX termination for both channels will be disabled.
0 – RX Detect disabled 1 – RX Detect enabled (Default) |
8 | DIR0 | 2 Level I | This pin along with DIR1 sets the data path signal direction format. Refer to Table 4 for signal direction formats. |
9 | URX2p | Diff I/O | Differential positive input/output for upstream facing RX2 port. |
10 | URX2n | Diff I/O | Differential negative input/output for upstream facing RX2 port. |
11 | DIR1 | 2 Level I/O | This pin along with DIR0 sets the data path signal direction format. Refer to Table 4 for signal direction formats. |
12 | UTX2p | Diff I/O | Differential positive input/output for upstream facing TX2 port. |
13 | UTX2n | Diff I/O | Differential negative input/output for upstream facing TX2 port. |
14 | VIO_SEL | 4 Level I/O | This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:
0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default) R = 3.3-V configuration I/O voltage, 1.8-V I2C interface F = 1.8-V configuration I/O voltage, 3.3-V I2C interface 1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface. |
15 | UTX1n | Diff I/O | Differential negative input/output for upstream facing TX1 port. |
16 | UTX1p | Diff I/O | Differential positive input/output for upstream facing TX1 port. |
17 | I2C_EN | 4 Level I | I2C Programming or Pin Strap Programming Select.
0 = GPIO Mode AUX Snoop enabled (I2C disabled) R = TI Test Mode (I2C enabled) F = GPIO Mode, AUX Snoop Disabled (I2C disabled) 1 = I2C enabled. |
18 | URX1n | Diff I/O | Differential negative input/output for upstream facing RX1 port. |
19 | URX1p | Diff I/O | Differential positive input/output for upstream facing RX1 port. |
20 | VCC | P | 3.3V Power Supply |
21 | FLIP/SCL | 2 Level I
(Failsafe) |
In GPIO mode, this is Flip control pin, otherwise this pin is I2C clock. |
22 | CTL0/SDA | 2 Level I
(Failsafe) |
In GPIO mode, this is a USB3.1 Switch control pin, otherwise this pin is I2C data. |
23 | CTL1 | 2 Level I
(PD) |
DP Alt mode Switch Control Pin. In GPIO mode, this pin will enable or disable DisplayPort functionality. Otherwise DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled. H = DisplayPort Enabled. In I2C mode, this pin is not used by device. |
24 | AUXp | I/O,
CMOS |
AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between the AC coupling capacitor and the AUXp pin if the TUSB544 is used on the DisplayPort source side, or a 1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB544 is used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB544 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug. |
25 | AUXn | I/O,
CMOS |
AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXn pin if the TUSB544 is used on the DisplayPort source side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB544 is used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB544 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug. |
26 | SBU2 | I/O,
CMOS |
SBU2. When the TUSB544 is used on the DisplayPort source side, this pin should be DC coupled to the SBU2 pin of the Type-C receptacle. When the TUSB544 is used on the DisplayPort sink side, this pin should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also recommended. |
27 | SBU1 | I/O,
CMOS |
SBU1. When the TUSB544 is used on the DisplayPort source side, this pin should be DC coupled to the SBU1 pin of the Type-C receptacle. When the TUSB544 is used on the DisplayPort sink side, this pin should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also recommended. |
28 | VCC | P | 3.3V Power Supply |
29 | DEQ1 | 4 Level I | This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2, DTX1, DTX2 receivers.
Up to 11 dB of EQ available. |
30 | DRX1p | Diff I/O | Differential positive input/output for downstream facing RX1 port. |
31 | DRX1n | Diff I/O | Differential negative input/output for downstream facing RX1 port. |
32 | HPDIN | 2 Level I (PD) | This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater than tCTL1_DEBOUNCE, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. |
33 | DTX1p | Diff I/O | Differential positive input/output for downstream facing TX1 port. |
34 | DTX1n | Diff I/O | Differential negative input/output for downstream facing TX1 port. |
35 | UEQ0/A0 | 4 Level I | This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. Up to 9.4 dB of EQ available. In I2C mode, this pin will also set TUSB544 I2C address. Refer to Table 10. |
36 | DTX2n | Diff I/O | Differential negative input/output for downstream facing TX2 port. |
37 | DTX2p | Diff I/O | Differential positive input/output for downstream facing TX2 port. |
38 | DEQ0 | 4 Level I | This pin along with DEQ1 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2, DTX1, DTX2 receivers.
Up to 11 dB of EQ available. |
39 | DRX2n | Diff I/O | Differential negative input/output for downstream facing RX2 port. |
40 | DRX2p | Diff I/O | Differential positive input/output for downstream facing RX2 port. |
Thermal Pad | GND | Ground |