JAJSCD2E august 2016 – march 2023 TUSB546-DCI
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN) | ||||||
IIH | High level input current | VCC = 3.6 V; VIN = 3.6 V | 20 | 80 | µA | |
IIL | Low level input current | VCC = 3.6 V; VIN = 0 V | –160 | -40 | µA | |
4-Level VTH | Threshold 0 / R | VCC = 3.3 V | 0.55 | V | ||
Threshold R/ Float | VCC = 3.3 V | 1.65 | V | |||
Threshold Float / 1 | VCC = 3.3 V | 2.7 | V | |||
RPU | Internal pull-up resistance | 35 | kΩ | |||
RPD | Internal pull-down resistance | 95 | kΩ | |||
2-State CMOS Input (CTL0, CTL1, FLIP, CAD_SNK, HPDIN) CTL1, CTL0 and FLIP are Failsafe. | ||||||
VIH | High-level input voltage | 2 | 3.6 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
RPD | Internal pull-down resistance for CTL1 | 500 | kΩ | |||
R(ENPD) | Internal pull-down resistance for CAD_SNK (pin 29), and HPDIN (pin 32) | 150 | kΩ | |||
IIH | High-level input current | VIN = 3.6 V | –25 | 25 | µA | |
IIL | Low-level input current | VIN = GND, VCC = 3.6 V | –25 | 25 | µA | |
I2C Control Pins SCL, SDA | ||||||
VIH | High-level input voltage | I2C_EN = 0 | 0.7 x V(I2C) | 3.6 | V | |
VIL | Low-level input voltage | I2C_EN = 0 | 0 | 0.3 x V(I2C) | V | |
VOL | Low-level output voltage | I2C_EN = 0; IOL = 3 mA | 0 | 0.4 | V | |
IOL | Low-level output current | I2C_EN = 0; VOL = 0.4 V | 20 | mA | ||
II(I2C) | Input current on SDA pin | 0.1 x V(I2C) < Input voltage < 3.3 V | –10 | 10 | µA | |
CI(I2C) | Input capacitance | 10 | pF | |||
C(I2C_FM+_BUS) | I2C bus capacitance for FM+ (1MHz) | 150 | pF | |||
C(I2C_FM_BUS) | I2C bus capacitance for FM (400kHz) | 150 | pF | |||
R(EXT_I2C_FM+) | External resistors on both SDA and SCL when operating at FM+ (1MHz) | C(I2C_FM+_BUS) = 150 pF | 620 | 820 | 910 | Ω |
R(EXT_I2C_FM) | External resistors on both SDA and SCL when operating at FM (400kHz) | C(I2C_FM_BUS) = 150 pF | 620 | 1500 | 2200 | Ω |