Use the following procedure to write
data to TUSB564-Q1 I2C registers (refer to Figure 7-2):
- The controller initiates a write operation by generating a
start condition (S), followed by the TUSB564-Q1
7-bit address and a zero-value “W/R” bit to indicate a write cycle.
- The TUSB564-Q1 acknowledges the
address cycle.
- The controller presents the register offset within TUSB564-Q1 to be written, consisting of one byte of
data, MSB-first.
- The TUSB564-Q1 acknowledges the
sub-address cycle.
- The controller presents the first byte of data to be
written to the I2C register.
- The TUSB564-Q1 acknowledges the
byte transfer.
- The controller can continue presenting additional bytes of
data to be written, with each byte transfer completing with an acknowledge
from the TUSB564-Q1.
- The controller terminates the write operation by generating
a stop condition (P).
Use the following procedure to read
the TUSB564-Q1 I2C registers without a repeated
Start (refer Figure 7-3).
- The controller initiates a read operation by generating a
start condition (S), followed by the TUSB564-Q1
7-bit address and a zero-value “W/R” bit to indicate a read cycle.
- The TUSB564-Q1 acknowledges the
7-bit address cycle.
- Following the acknowledge the controller continues sending
clock.
- The TUSB564-Q1 transmit the
contents of the memory registers MSB-first starting at register 00h or last
read register offset+1. If a write to the I2C register occurred
prior to the read, then the TUSB564-Q1 shall start
at the register offset specified in the write.
- The TUSB564-Q1 waits for either an
acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each
byte transfer; the I2C controller acknowledges reception of each
data byte transfer.
- If an ACK is received, the TUSB564-Q1 transmits the next byte of data as long as controller
provides the clock. If a NAK is received, the TUSB564-Q1 stops providing data and waits for a stop condition
(P).
- The controller terminates the write operation by
generating a stop condition (P).
Use the following procedure to read
the TUSB564-Q1 I2C registers with a repeated
Start (refer Figure 7-4).
- The controller initiates a read operation by generating a
start condition (S), followed by the TUSB564-Q1
7-bit address and a zero-value “W/R” bit to indicate a write cycle.
- The TUSB564-Q1 acknowledges the
7-bit address cycle.
- The controller presents the register offset within TUSB564-Q1 to be written, consisting of one byte of
data, MSB-first.
- The TUSB564-Q1 acknowledges the
register offset cycle.
- The controller presents a repeated start condition
(Sr).
- The controller initiates a read operation by generating a
start condition (S), followed by the TUSB564-Q1
7-bit address and a one-value “W/R” bit to indicate a read cycle.
- The TUSB564-Q1 acknowledges the
7-bit address cycle.
- The TUSB564-Q1 transmit the
contents of the memory registers MSB-first starting at the register
offset.
- The TUSB564-Q1 shall wait for
either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller
after each byte transfer; the I2C controller acknowledges
reception of each data byte transfer.
- If an ACK is received, the TUSB564-Q1 transmits the next byte of data as long as controller
provides the clock. If a NAK is received, the TUSB564-Q1 stops providing data and waits for a stop condition
(P).
- The controller terminates the read operation by generating
a stop condition (P).
Use the following procedure to set a
starting sub-address for I2C reads (refer to Figure 7-5).
- The controller initiates a write operation by generating a
start condition (S), followed by the TUSB564-Q1
7-bit address and a zero-value “W/R” bit to indicate a write cycle.
- The TUSB564-Q1 acknowledges the
address cycle.
- The controller presents the register offset within TUSB564-Q1 to be written, consisting of one byte of
data, MSB-first.
- The TUSB564-Q1 acknowledges the
register offset cycle.
- The controller terminates the write operation by
generating a stop condition (P).
Note:
After initial power-up, if no
register offset is included for the read procedure (refer to Figure 7-3), then reads start at register offset 00h and continue byte
by byte through the registers until the I2C controller terminates the
read operation. During a read operation, the TUSB564-Q1
auto-increments the I2C internal register address of the last byte
transferred independent of whether or not an ACK was received from the
I2C controller.
Software must only access (read or write) addresses detailed in this document.
Accessing reserved or undocumented addresses can result in TUSB564-Q1
entering an undefined state.