JAJSNA2A May   2024  – September 2024 TUSB564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.1 Device Configuration in GPIO Mode

The TUSB564-Q1 is in GPIO configuration when I2C_EN = "0". The TUSB564-Q1 supports the following configurations: USB only, 2 DisplayPort lanes + USB, or 4 DisplayPort lanes (no USB). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB only, 2 lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 7-2. The AUXp or AUXn to SBU1 or SBU2 mapping is controlled based on Table 7-3.

After power up (VCC from 0V to 3.3V), the TUSB564-Q1 defaults to USB mode. The USB PD controller upon detecting no device attached to Type-C port must take TUSB564-Q1 out of USB mode by transitioning the CTL0 pin from L to H and back to L.

Table 7-2 GPIO Configuration Control
CTL1 PINCTL0 PINFLIP PINCONFIGURATIONVESA DisplayPort ALT MODE
UFP_D CONFIGURATION
LLLPower Down—
LLHPower Down—
LHLOne Port USB – No Flip—
LHHOne Port USB – With Flip—
HLL4 Lane DP – No FlipC
HLH4 Lane DP – With FlipC
HHLOne Port USB + 2 Lane DP – No FlipD
HHHOne Port USB + 2 Lane DP – With FlipD
Table 7-3 GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PINFLIP PINMAPPING
HLSBU1 → AUXn
SBU2 → AUXp
HHSBU2 → AUXn
SBU1 → AUXp
L > 2msXOpen

Table 7-4 details the TUSB564-Q1 MUX routing. This table is valid for both I2C and GPIO configuration modes.

Table 7-4 INPUT to OUTPUT Mapping
CTL1 PINCTL0 PINFLIP PINFROMTO
INPUT PINOUTPUT PIN
LLLNANA
LLHNANA
LHLRX1pSSRXp
RX1nSSRXn
SSTXpTX1p
SSTXnTX1n
LHHRX2pSSRXp
RX2nSSRXn
SSTXpTX2p
SSTXnTX2n
HLLTX2pDP0p
TX2nDP0n
RX2pDP1p
RX2nDP1n
RX1pDP2p
RX1nDP2n
TX1pDP3p
TX1nDP3n
HLHTX1pDP0p
TX1nDP0n
RX1pDP1p
RX1nDP1n
RX2pDP2p
RX2nDP2n
TX2pDP3p
TX2nDP3n
HHLRX1pSSRXp
RX1nSSRXn
SSTXpTX1p
SSTXnTX1n
TX2pDP0p
TX2nDP0n
RX2pDP1p
RX2nDP1n
HHHRX2pSSRXp
RX2nSSRXn
SSTXpTX2p
SSTXnTX2n
TX1pDP0p
TX1nDP0n
RX1pDP1p
RX1nDP1n