JAJSNA2A May 2024 – September 2024 TUSB564-Q1
PRODUCTION DATA
Each of the TUSB564-Q1 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7-7 details the gain value for each available combination when TUSB564-Q1 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R = 01, F = 10, 1 = 11.
| EQUALIZATION SETTING # | USB3.1 UPSTREAM FACING PORTS | USB 3.1 DOWNSTREAM FACING PORT | ALL DISPLAYPORT LANES | ||||||
|---|---|---|---|---|---|---|---|---|---|
| EQ1 PIN LEVEL | EQ0 PIN LEVEL | EQ GAIN AT 2.5GHz (dB) | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ GAIN AT 2.5GHz (dB) | DPEQ1 PIN LEVEL | DPEQ0 PIN LEVEL | EQ GAIN AT 4.05GHz (dB) | |
| 0 | 0 | 0 | –0.7 | 0 | 0 | -0.9 | 0 | 0 | 1.0 |
| 1 | 0 | R | 1.8 | 0 | R | 0.2 | 0 | R | 3.0 |
| 2 | 0 | F | 2.7 | 0 | F | 1.1 | 0 | F | 4.4 |
| 3 | 0 | 1 | 3.7 | 0 | 1 | 2.2 | 0 | 1 | 5.8 |
| 4 | R | 0 | 4.6 | R | 0 | 3.0 | R | 0 | 6.8 |
| 5 | R | R | 5.5 | R | R | 4.0 | R | R | 8.0 |
| 6 | R | F | 6.3 | R | F | 4.8 | R | F | 8.8 |
| 7 | R | 1 | 7.0 | R | 1 | 5.6 | R | 1 | 9.6 |
| 8 | F | 0 | 7.8 | F | 0 | 6.4 | F | 0 | 10.4 |
| 9 | F | R | 8.5 | F | R | 7.0 | F | R | 11.0 |
| 10 | F | F | 9.1 | F | F | 7.6 | F | F | 11.6 |
| 11 | F | 1 | 9.7 | F | 1 | 8.2 | F | 1 | 12.1 |
| 12 | 1 | 0 | 10.1 | 1 | 0 | 8.7 | 1 | 0 | 12.5 |
| 13 | 1 | R | 10.7 | 1 | R | 9.2 | 1 | R | 13.0 |
| 14 | 1 | F | 11.1 | 1 | F | 9.7 | 1 | F | 13.4 |
| 15 | 1 | 1 | 11.6 | 1 | 1 | 10.2 | 1 | 1 | 13.7 |