JAJSNA2A May   2024  – September 2024 TUSB564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PCC-ACTIVE-USB Average active power in USB-only mode while in U0 CTL1 = L; CTL0 = H; Link in U0 at 5Gbps; 340 mW
PCC-ACTIVE-USB-DP Average active power in USB + 2 lane DP mode CTL1 = H; CTL0 = H; USB in U0 at 5Gbps;  DP at 8.1Gbps; 670 mW
PCC-ACTIVE-DP Average active power in 4 lane DP mode CTL1 = H; CTL0 = L; Four DP lanes at 8.1Gbps 640 mW
PCC-NC-USB Average power in USB mode while in disconnect state. CTL1 = L; CTL0 = H; No USB device detected; 2.5 mW
PCC-U2U3 Average power in USB mode while in U2/U3 state CTL1 = L; CTL0 = H; Link in U2 or U3; 2.5 mW
PCC-SHUTDOWN Average power in shutdown mode. CTL1 = L; CTL0 = L; I2C_EN = "0"; 0.7 mW
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIH High-level input current VCC = 3.6V; VIN = 3.6V 20 80 µA
IIL Low-level input current VCC = 3.6V; VIN = 0V –160 –40 µA
4-Level VTH Threshold 0 / R VCC = 3.3V 0.59 V
Threshold R/ Float VCC = 3.3V 1.65 V
Threshold Float / 1 VCC = 3.3V 2.7 V
RPU Internal pullup resistance 45 kΩ
RPD Internal pulldown resistance 95 kΩ
2-State CMOS Input (EN, FLIP, CTL0, CTL1, HPDIN) CTL1, CTL0 and FLIP are Failsafe
VIH High-level input voltage 2.2 3.6 V
VIL Low-level input voltage 0 0.8 V
RPD Internal pull-down resistance for FLIP, CTL0, and EN. 500 kΩ
RPD-CTL1 Internal pull-down resistance for CTL1 395 kΩ
IIH-EN High-level input current for EN pin VIN = 3.6V 4 12 µA
IIL-EN Low-level input current for EN pin VIN = GND, VCC = 3.6V –1 1 µA
IIH-FLIP High-level input current for FLIP pin VIN = 3.6V 4 12 µA
IIL-FLIP Low-level input current for FLIP pin VIN = GND, VCC = 3.6V –1 1 µA
IIH-CTL0 High-level input current for CTL0 pin VIN = 3.6V 4 12 µA
IIL-CTL0 Low-level input current for CTL0 pin VIN = GND, VCC = 3.6V –1 1 µA
IIH-CTL1 High-level input current for CTL1 pin VIN = 3.6V 4 12 µA
IIL-CTL1 Low-level input current for CTL1 pin VIN = GND, VCC = 3.6V –1 1 µA
IIH-HPDIN High-level input current for HPD pin VIN = 3.6V 0.5 5 µA
IIL-HPDIN Low-level input current for HPD pin VIN = GND, VCC = 3.6V –1 1 µA
I2C Control Pins SCL, SDA
VIH High-level input voltage I2C_EN = "1" or "R" (3.3V I2C levels) 2.2 3.6 V
VIL Low-level input voltage I2C_EN = "1" or "R" (3.3V I2C levels) 0 0.8 V
VIH High-level input voltage I2C_EN = "F"  (1.8V I2C levels) 1.2 3.6 V
VIL Low-level input voltage I2C_EN = "F"  (1.8V I2C levels) 0 0.4 V
VOL Low-level output voltage I2C_EN ! = "0"; IOL = 3mA 0 0.4 V
IOL Low-level output current I2C_EN ! = "0"; VOL = 0.4V 20 mA
Ii_I2C Input current on SDA pin 0.1 × VI2C < Input voltage < 3.3V –10 10 µA
Ci_I2C Input capacitance 10 pF
USB Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
VRX-DIFF-PP Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 1200 mVppd
VRX-DC-CM Common-mode voltage bias in the receiver (DC) 0 V
RRX-DIFF-DC Differential input impedance (DC) Present after a USB3 device is detected on TXP/TXN 72 120 Ω
RRX-CM-DC Receiver DC common mode impedance Present after a USB3 device is detected on TXP/TXN 18 30 Ω
ZRX-HIGH-IMP-DC-POS Common-mode input impedance with termination disabled (DC) Present when no USB3 device is detected on TXP/TXN. Measured over the range of 0V to 500mV with respect to GND. 25 kΩ
VSIGNAL-DET-DIFF-PP Input differential peak-to-peak signal detect assert level At 5Gbps, No loss and bit rate PRBS7 pattern 80 mVppd
VRX-IDLE-DET-DIFF-PP Input differential peak-to-peak signal detect de-assert level At 5Gbps, No loss and bit rate PRBS7 pattern 60 mVppd
VRX-LFPS-DET-DIFF-PP Low-frequency periodic signaling (LFPS) detect threshold 25℃ ≤ TA ≤ 105℃; Below the minimum is squelched. Tested at 25MHz and 300mVppd VIN. 100 300 mVppd
RLRX-DIFF Differential return loss 50MHz to 1.25GHz at 90Ω; Lowest EQ setting; FLIP = L; –23 dB
RLRX-DIFF Differential return loss 2.5GHz at 90Ω; Lowest EQ setting; FLIP = L; –22 dB
RLRX-CM Common-mode return loss 50MHz to 2.5GHz at 90Ω; Lowest EQ setting; FLIP = L; –13 dB
EQSS Receiver equalization for RX1/2 receivers at maximum setting At 2.5GHz; FLIP = L; 11.6 dB
EQSS Receiver equalization for SSTX receiver at maximum setting At 2.5GHz; FLIP = L; 10 dB
USB Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX-DIFF-PP Transmitter dynamic differential voltage swing range.   1300   mVppd
VTX-RCV-DETECT Amount of voltage change allowed during Receiver Detection At 3.3V     600 mV
VTX-CM-IDLE-DELTA Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS Measured at the connector side of the AC-coupling capacitor with 50Ω load –600   600 mV
VTX-DC-CM Common-mode voltage bias in the transmitter (DC) In U0; 1.5   2.1 V
VTX-CM-AC-PP-ACTIVE TX AC common-mode voltage active At 3.3V; Maximum mismatch from Txp+Txn for both time and amplitude   100 mVpp
VTX-IDLE-DIFF-AC-PP AC electrical idle differential peak-to-peak output voltage At package pins after high-pass filter (HPF) to remove DC component; HPF = 1/LPF; No AC or DC signals are applied at RX terminals; 0   10 mV
VTX-IDLE-DIFF-DC DC electrical idle differential output voltage At package pins after low-pass filter (LPF) to remove AC component; LPF = 1/HPF; No AC or DC signals are applied at RX terminals; 0   10 mV
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute DC common-mode voltage between U1 and U0 At package pin     200 mV
RTX-DIFF Differential impedance of the driver 75   120 Ω
RTX-CM Common-mode impedance of the driver Measured with respect to AC ground over 0V to 500mV 18   30 Ω
CAC-COUPLING External AC-coupling capacitor 75   265 nF
ITX-SHORT TX short-circuit current TX+/- shorted to GND     67 mA
RLTX-DIFF Differential return loss (SDD22) 50MHz to 1.25GHz at 90Ω; Lowest EQ setting; FLIP = L;   –25   dB
RLTX-DIFF-2.5G Differential return loss (SDD22) 2.5GHz at 90Ω; Lowest EQ setting; FLIP = L;   –12   dB
RLTX-CM Common-mode return loss (SCC22) 50MHz to 2.5GHz at 90Ω; Lowest EQ setting; FLIP = L;   –14   dB
AC Electrical Characteristics
Crosstalk Differential crosstalk between TX and RX signal pairs At 2.5GHz; FLIP = L;   –45   dB
GLF Low-frequency voltage gain. At 100MHz, 600mVpp VID –0.25 0.6 1.5 dB
GLF_LFPS_TX1/2 Low-frequency voltage gain for SSTX –> TX1/TX2 path At 10MHz to 50MHz sine wave; 1.0Vpp VID; EQ = 0; FLIP = 0 and 1; –0.5 0.8 1.6 dB
CP1 dB-LF Low-frequency –1dB compression point At 100MHz, 200mVpp < VID < 2000mVpp 1000 mVpp
CP1 dB-HF High-frequency –1dB compression point At 2.5GHz, 200mVpp < VID < 2000mVpp   1000   mVpp
DJ_5G TX output deterministic jitter 200mVpp < VID < 2000mVpp, PRBS7, 5Gbps, 10dB pre-channel and 1dB post-channel, Optimal EQ setting   0.025   UIpp
DJ_8.1G TX output deterministic jitter 200mVpp < VID < 2000mVpp, PRBS7, 8.1Gbps, 10dB pre-channel and 1dB post-channel, Optimal EQ setting   0.03   UIpp
DisplayPort Receiver (TX1P/N, TX2P/N, RX1P/N, RX2P/N)
VID_PP Peak-to-peak input differential dynamic voltage range   1400   mVppd
VIC Input common-mode voltage   0 V
CAC External AC-coupling capacitor   75   265 nF
EQDP Receiver equalizer at maximum setting At 4.05GHz;   13.7   dB
dR Data rate HBR3   8.1 Gbps
Rtx Input termination resistance   80 100 120 Ω
DisplayPort Transmitter (DP[3:0]P/N)
VTX-DIFFPP VOD dynamic range     1300   mVppd
ITX-SHORT TX short-circuit current TX+/- shorted to GND     67 mA
VDPTX-DC-CM Common-mode voltage bias in the transmitter (DC) 1.5 2.2 V
RDPTX Differential impedance of the driver 75 120 Ω
AUXP/N and SBU1/2
RON Output ON resistance VCC = 3.3V; VIN = 0V to 0.4V for AUXP; VIN = 2.7V to 3.6V for AUXN   5 10 Ω
RON-MISMATCH ΔON resistance mismatch within pair VCC = 3.3V; VIN = 0V to 0.4V for AUXP; VIN= 2.7V to 3.6V for AUXN     1.5 Ω
RON_FLAT ON resistance flatness (RONmax–RON min) measured at identical VCC and temperature VCC = 3.3V; VIN = 0V to 0.4V for AUXP; VIN = 2.7V to 3.6V for AUXN     2 Ω
VAUXP_DC_CM AUX channel DC common-mode voltage for AUXP and SBU2. VCC = 3.3V 0   0.4 V
VAUXN_DC_CM AUX channel DC common-mode voltage for AUXN and SBU1 VCC = 3.3V 2.7   3.6 V
CAUX_ON ON-state capacitance VCC = 3.3V; CTL1 = 1; VIN = 0V or 3.3V   4 7 pF
CAUX_OFF OFF-state capacitance VCC = 3.3V; CTL1 = 0; VIN = 0V or 3.3V   3 6 pF