JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Device Control 2 Register controls PCI Express device specific parameters.
PCI register offset: 98h
Register type: Read-only, Read/Write
Default value: 0800h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:5 | RSVD | r | Reserved. Returns zeros when read. |
4 | CPTL_TO_DIS | rw | Completion Timeout Disable. |
3:0 | CPLT_TO_VALUE | r | Completion Timeout Value. This field is read only 0000b indicating that completion timeout programming is not supported. |