JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset.
Note: For Pass 1.0 of the TUSB73X0 design, this register is read only zeros and has no effect.
PCI register offset: DCh
Register type: Read-Only, Read/Write
Default value: 0000 001Bh
Bit No. | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
31:6 | RSVD | r | Reserved. Returns zeros when read. |
5:3 | L1_LATENCY(1) | rw | L1 Maximum Exit Latency. This field is used to program the maximum acceptable latency when exiting the L1 state. This is used to set the L1 Acceptable Latency field in the Device capabilities register. 000 – Less than 1µs 001 – 1 µs up to less than 2 µs 010 – 2 µs up to less than 4 µs 011 – 4 µs up to less than 8 µs (default) 100 – 8 µs up to less than 16 µs 101 – 16 µs up to less than 32 µs 110 – 32 µs to 64 µs 111 – more than 64 µs |
2:0 | L0s_LATENCY(1) | rw | L0s Maximum Exit Latency. This field is used to program the maximum acceptable latency when exiting the L0s state. This is used to set the L0s Acceptable Latency field in the Device capabilities register. 000 – Less than 64 ns 001 – 64 ns up to less than 128 ns 010 – 128 ns up to less than 256 ns 011 – 256 ns up to less than 512 ns (default) 100 – 512 ns up to less than 1 µs 101 – 1 µs up to less than 2 µs 110 – 2 µs to 4 µs 111 – more than 4 µs |