JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Link Control 2 Register indicates is used to control link specific behavior.
PCI register offset: A0h
Register type: Read-only, Read/Write
Default value: 0000h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:13 | RSVD | r | Reserved. Returns zeros when read. |
12 | COMPLIANCE_DEEMPH(1) | rw | Compliance De-Emphasis. This bit is sticky and is only reset by a Global Reset. |
11 | COMPLIANCE_SOS(1) | rw | Compliance SOS. This bit is sticky and is only reset by a Global Reset. |
10 | ENT_MOD_COMPLIANCE(1) | rw | Enter Modified Compliance. This bit is sticky and is only reset by a Global Reset. |
9:7 | TRANSMIT_MARGIN(1) | rw | Transmit Margin. This bit is sticky and is only reset by a Global Reset. |
6 | SEL_DEEMPH | r | Selectable De-Emphasis. This bit has no function and is read only zero. |
5 | HW_AUTO_SPEED_DIS | r | Hardware Autonomous Speed Disable. This bit is read only zero because this function is not supported. |
4 | ENTER_COMPL(1) | rw | Enter Compliance. This bit is sticky and is only reset by a Global Reset. |
3:0 | TGT_LINK_SPEED(1) | rw | Target Link Speed. This bit is sticky and is only reset by a Global Reset. |