JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
This register is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written to this register, the length of the frame is adjusted for all USB buses implemented by the TUSB73X0. This register is only reset by a Global Reset.
PCI register offset: 61h
Register type: Read/Write
Default value: 20h
Bit No. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
7:6 | RSVD | r | Reserved. Return zeros when read. |
5:0 | FRAME_LENGTH(1) | rw | Frame Length Timing Value. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time is equal to 59488 plus the value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. |