JAJSOK5 データシート

JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RKM|100
- MPQF258B

サーマルパッド・メカニカル・データ

RKM|100
- QFND273C

発注情報

8.1.64 USB Control Register

This register is a read/write register is used to control USB settings in the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset.

PCI register offset: E0h

Default value: 0000 0000h

Table 8-99 PCI Register E0h

Bit No.	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Reset State	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit No.	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset State	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 8-100 USB Control Register Description

BIT	FIELD NAME	ACCESS	DESCRIPTION
31	USB_SPREAD_DIS⁽¹⁾	rw	USB Spread Spectrum Disable. When this bit is set to 1, spread spectrum generation for the USB 3.0 clock is disabled.
30	FREQ_SEL_EN⁽²⁾	rw	Frequency Select Enable. When this bit is set to 1, the oscillator is restarted. This bit can only be written to once after power up.
29:24	PLL_FREQ_SEL⁽²⁾	r	PLL Frequency Select. If the FREQSEL pin is 1, then the value in this field controls the Frequency Select inputs to the PLL. In addition, the frequency selector inputs to the Oscillator are set appropriately for the frequency selected. If the FREQSEL pin is 0, then this field has no effect. Once the FREQ_SEL_EN bit has been set, this field will be locked and cannot be changed.
23	HIDE_MSIX⁽¹⁾	rw	Hide MSI-X. When this bit is set, the Next Item Pointer Register (offset 71h) for the PCI Express Capability is set to 00h, and BAR2 (offset 18h) and BAR3 (offset 1Ch) are only zeros.
22	PWRON_POLARITY⁽²⁾	rw	PWRONx Polarity. When this bit is 0 (default), the PWRONx# pins are active low and their internal pull-down resistors are enabled. When this bit is 1, the PWRONx# pins are active high and their internal pull-down resistors are disabled.
21:17	RSVD	r	Reserved. Returns zero when read.
16	PPC_NOT_PRESENT⁽¹⁾	rw	Port Power Control Not Present. When this bit is 0, the TUSB73X0 forces the PPC bit to 1 in the Host Controller Capability Parameters, indicating that the system supports port power switches. When this bit is set to 1, the TUSB73X0 forces the PPC bit to 0 in the Host Controller Capability Parameters, indicating that the system does not support port power switches.
15:12	RSVD⁽¹⁾	rw	Reserved. Returns zeros when read.
11	PORT4_DIS⁽¹⁾	rw	USB Port 4 Disable. When this bit is set to 1, port 4 of the TUSB73X0 is disabled. For the TUSB7320 Port 4 is not present and this bit has no effect.
10	PORT3_DIS⁽¹⁾	rw	USB Port 3 Disable. When this bit is set to 1, port 3 of the TUSB73X0 is disabled. For the TUSB7320 Port 3 is not present and this bit has no effect.
9	PORT2_DIS⁽¹⁾	rw	USB Port 2 Disable. When this bit is set to 1, port 2 of the TUSB73X0 is disabled.
8	PORT1_DIS⁽¹⁾	rw	USB Port 1 Disable. When this bit is set to 1, port 1 of the TUSB73X0 is disabled.
7	USB3_PORT4_NON_REM⁽¹⁾	rw	USB 3.0 Port 4 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect.
6	USB3_PORT3_NON_REM⁽¹⁾	rw	USB 3.0 Port 3 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect.
5	USB3_PORT2_NON_REM⁽¹⁾	rw	USB 3.0 Port 2 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 2.
4	USB3_PORT1_NON_REM⁽¹⁾	rw	USB 3.0 Port 1 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 1.
3	USB2_PORT4_NON_REM⁽¹⁾	rw	USB 2.0 Port 4 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect.
2	USB2_PORT3_NON_REM⁽¹⁾	rw	USB 2.0 Port 3 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect.
1	USB2_PORT2_NON_REM⁽¹⁾	rw	USB 2.0 Port 2 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 2.
0	USB2_PORT1_NON_REM⁽¹⁾	rw	USB 2.0 Port 1 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 1.

(1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.

(2) This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated power-on-reset.