JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see Host Controller Structural Parameters 1).
Operational Base register offset: 404h + (10h × (n-1))), where n = Port Number
Register type: Read-Only, Read/Write
Default value: 0000 0000h
Bit No. | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
31:28 | PORT_TEST_CTRL | rw | Port Test Control. |
27:16 | RSVD | r | Reserved. Returns zeros when read. |
15:8 | L1_DEV_SLOT | rw | L1 Device Slot. |
7:4 | HIRD | rw | Host Initiated Resume Duration. |
3 | RWE | rw | Remote Wake Enable. |
2:0 | L1S | r | L1 Status. |