JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The register is used to control the sending of MSI messages.
PCI register offset: 4Ah
Register type: Read/Write, Read-only
Default value: 0086h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:8 | RSVD | r | Reserved. Returns zeros when read. |
8 | PVM_CAP | r | Per-vector Masking Capable. This bit is read only 0 indicating that the TUSB73X0 does not support per-vector masking. |
7 | 64CAP | r | 64 Bit Message Capability. This bit is read only 1 indicating that the TUSB73X0 supports 64 bit MSI message addressing. |
6:4 | MM_EN | rw | Multiple Message Enable. This bit indicates the number of distinct messages that the TUSB73X0 is allowed to generate. 000 – 1 Message (All interrupters mapped to the same message) 001 – 2 Messages (Interrupters 0, 2, 4, and 6 mapped to message 0 and Interrupters 1, 3, 5, and 7 mapped to message 1) 010 – 4 Messages (Interrupters 0 and 4 mapped to message 0, Interrupters 1 and 5 mapped to message 1, Interrupters 2 and 6 mapped to message 2, Interrupters 3 and 7 mapped to message 3) 011 – 8 Messages (Interrupter # mapped to corresponding message #) 100 – 16 Messages (Interrupter # mapped to corresponding message #) 101 – 32 Messages (Interrupter # mapped to corresponding message #) 110 – Reserved111 – Reserved |
3:1 | MM_CAP | r | Multiple Message Capabilities. This field indicates the number of distinct messages that TUSB73X0 is capable of generating. This field is read only 011 indicating that the TUSB73X0 can signal 8 distinct messages. |
0 | MSI_EN | rw | MSI Enable. This bit is used to enable MSI interrupt signaling. MSI signaling must be enabled by software for the TUSB73X0 to signal an MSI 0 – MSI signaling is prohibited 1 – MSI signaling is enabled |