JAJSOK5Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The read-only register indicates the capabilities of the TUSB73X0 related to PCI power management.
PCI register offset: 42h
Register type: Read-only
Default value: xxx3h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | x | 1 | 1 | 1 | 1 | 1 | 1 | x | x | x | 0 | 0 | 0 | 0 | 1 | 1 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:11 | PME_SUPPORT | r | PME# support. This five-bit field indicates the power states from which the TUSB73X0 may assert PME#. If the AUX_DET pin is 1, this field is 11111. If the AUX_DET pin is 0, this field is 01111. |
10 | D2_SUPPORT | r | This bit returns a 1 when read, indicating that the function supports the D2 device power state. |
9 | D1_SUPPORT | r | This bit returns a 1 when read, indicating that the function supports the D1 device power state. |
8:6 | AUX_CURRENT | r | 3.3 Vaux auxiliary current requirements. If the AUX_DET pin is 1, this field is 010. If the AUX_DET pin is 0, this field is 000. |
5 | DSI | r | Device Specific Initialization. This bit returns 0 when read, indicating that the TUSB73X0 does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. |
4 | RSVD | r | Reserved. Returns zero when read. |
3 | PME_CLK | r | PME# Clock. |
2:0 | PM_VERSION | r | Power Mgmt Version. This field returns 3’b011 indicating Rev 1.2 compatibility. |