7 | customStrings | RW | Custom Strings Enable. When this bit is set and the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads the string registers from the contents of the EEPROM. When set and the TUSB8040A1 is in SMBUS mode, the string registers may written by an SMBus host. This bit defaults to 0. |
6 | customSernum | RW | Custom Serial Number Enable. When this bit is set and the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads the serial number register from the contents of the EEPROM. When set and the TUSB8040A1 is in SMBUS mode, the Serial Number registers may written by an SMBus host. This bit defaults to 0. |
5 | u1u2Disable | RW | U1 U2 Disable. When this bit is set the TUSB8040A1 will not initiate or accept any U1 or U2 requests on any port, upstream or downstream, unless it receives or sends a Force_LinkPM_Accept LMP. After receiving or sending an FLPMA LMP, it will continue to enable U1 and U2 according to USB 3.0 protocol until it gets a power-on reset or is disconnected on its upstream port. This bit is loaded at the de-assertion of reset with the value of the SDA_SMBDAT terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be over-written by an SMBus host. |
4 | portIndz | RW | Port Indicator Status. This bit shall be loaded at the de-assertion of reset with the value of PORTINDz_SMBA3 terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be overwritten by an SMBus host. |
3 | ganged | RW | Ganged. This bit shall be loaded at the de-assertion of reset with the value of GANGEd_SMBA2 terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be overwritten by an SMBus host. |
2 | fullPwrMgmtz | RW | Full Power Management. This bit is loaded at the de-assertion of reset with the value of the FULLPWRMGMTz_SMBA1 terminal. When this bit is 0, power switching and over-current detection is supported whether bus- or self-powered. When the bit is 1 and the device is bus powered, power switching is supported but over-current detection is not supported. When the bit is 1 and the device is self-powered over-current detection is supported but power switching is not supported. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be over-written by an SMBus host. |
1 | u1u2TimerOvr | RW | U1 U2 Timer Override. When this bit is set the TUSB8040A1 will override the downstream ports u1/u2 timeout values set by software. If software sets a value in the range of 1-FF, the TUSB8040A1 will use the value FF. If software sets a value of 0, the TUSB8040A1 will use the value 0.This bit is loaded at the de-assertion of reset with the value of the SCL_SMBCLK terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be over-written by an SMBus host. |
0 | RSVD | RO | Reserved. Read only, returns 0 when read. |