JAJSQP2D february   2013  – july 2023 TUSB8040A1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-9FC00080-214A-41B8-A47D-B9F7BA87DE22/SLLSE42922
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 3.3-V I/O Electrical Characteristics
    6. 6.6 Hub Input Supply Current
    7. 6.7 Timing and Switching Characteristics
      1. 6.7.1 Clock Generation
      2. 6.7.2 Crystal Requirements
      3. 6.7.3 Input Clock Requirements
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
    4. 7.4 I2C EEPROM Operation
    5. 7.5 SMBus Target Operation
    6. 7.6 Configuration Registers
      1. 7.6.1  ROM Signature Register
      2. 7.6.2  Vendor ID LSB Register
      3. 7.6.3  Vendor ID MSB Register
      4. 7.6.4  Product ID LSB Register
      5. 7.6.5  Product ID MSB Register
      6. 7.6.6  Device Configuration Register
      7. 7.6.7  Battery Charging Support Register
      8. 7.6.8  Device Removable Configuration Register
      9. 7.6.9  Port Used Configuration Register
      10. 7.6.10 Reserved Register
      11. 7.6.11 Reserved Register
      12. 7.6.12 Language ID LSB Register
      13. 7.6.13 Language ID MSB Register
      14. 7.6.14 Serial Number String Length Register
      15. 7.6.15 Manufacturer String Length Register
      16. 7.6.16 Product String Length Register
      17. 7.6.17 Reserved Register
      18. 7.6.18 Serial Number Registers
      19. 7.6.19 Manufacturer String Registers
      20. 7.6.20 Product String Registers
      21. 7.6.21 Additional Feature Configuration Register
      22. 7.6.22 Reserved Register
      23. 7.6.23 Reserved Register
      24. 7.6.24 Device Status and Command Register
  9. 8Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Upstream Port Implementation
        2. 8.2.2.2 Downstream Port 1 Implementation
        3. 8.2.2.3 Downstream Port 2 Implementation
        4. 8.2.2.4 Downstream Port 3 Implementation
        5. 8.2.2.5 Downstream Port 4 Implementation
        6. 8.2.2.6 VBUS Power Switch Implementation
        7. 8.2.2.7 Clock, Reset, I2C/SMBUS, and Misc
        8. 8.2.2.8 Power Implementation
      3. 8.2.3 Application Curve
      4. 8.2.4 Power Supply Recommendations
        1. 8.2.4.1 Power Up and Reset
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
          1. 8.2.5.1.1 Part Placement
          2. 8.2.5.1.2 Board Layout Considerations
            1. 8.2.5.1.2.1  RKM Package – QFN (Quad Flat No-Lead)
            2. 8.2.5.1.2.2  Impedance
            3. 8.2.5.1.2.3  Critical Signals
            4. 8.2.5.1.2.4  Crystal
            5. 8.2.5.1.2.5  USB Interface
            6. 8.2.5.1.2.6  Differential Pair Signals
              1. 8.2.5.1.2.6.1 Internal Bond Wire Mismatch
            7. 8.2.5.1.2.7  Port Connectors
            8. 8.2.5.1.2.8  Reset Terminals
            9. 8.2.5.1.2.9  Miscellaneous Terminals
            10. 8.2.5.1.2.10 Power Control and Battery Charging Terminals
            11. 8.2.5.1.2.11 USB 2.0 Port Indicator LED Terminals
          3. 8.2.5.1.3 Power
            1. 8.2.5.1.3.1 Power
            2. 8.2.5.1.3.2 Downstream Port Power
            3. 8.2.5.1.3.3 Ground
        2. 8.2.5.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-B75656C7-8EB3-4108-9555-49E96525DA24-low.gif Figure 5-1 100-Pin TUSB8040A1 RKM Package, 100-Pin WQFN (Top View)
Table 5-1 Signal Descriptions
TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PD, PU Internal pull-down/pull-up
PT Passive pass through
P Power Supply
G Ground
Table 5-2 Clock and Reset Signals
SIGNAL NAME TYPE PIN NO. DESCRIPTION
GRSTz I, PU A18 Global power reset. This reset brings all of the TUSB8040A1 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional. GRSTz should be asserted a minimum of 3 ms after all power rails are valid at the device.
XI I A49 Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
XO O A48 Crystal output. This pin is crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
VSSOSC I B45 Oscillator return. If using a crystal, the load capacitors should use this signal as the return path and it should not be connected to the PCB ground. If using an oscillator, this terminal should be connected to PCB Ground.
Table 5-3 USB Upstream Signals
SIGNAL NAME TYPE PIN NO. DESCRIPTION
USB_SSTXP_UP O B39 USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP O A42 USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP I A44 USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP I B40 USB SuperSpeed receiver differential pair (negative)
USB_DP_UP I/O A46 USB high-speed differential transceiver (positive)
USB_DM_UP I/O B42 USB high-speed differential transceiver (negative)
USB_R1 PT A50 Precision resistor reference. A 9.09-kΩ ±1% resistor should be connected between USB_R1 and USB_R1RTN.
USB_R1RTN PT B47 Precision resistor reference return
USB_VBUS I B44 USB Upstream port power monitor. The USB_VBUS input is a 1.2-V I/O cell and requires a voltage divider to prevent damage to the input. The signal USB_VBUS must be connected to VBUS through a 90.9-kΩ ±1% resistor, and to signal ground through a 10-kΩ ±1% resistor. This allows the input to detect VBUS present from a minimum of 4 V and sustain a maximum VBUS voltage up to 10 V (applied to the voltage divider).
Table 5-4 USB Downstream Signals
SIGNAL NAME TYPE PIN NO. DESCRIPTION
USB_SSTXP_DN0 O B4 USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN0 O A4 USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN0 I B3 USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN0 I A3 USB SuperSpeed receiver differential pair (negative)
USB_DP_DN0 I/O B1 USB high-speed differential transceiver (positive)
USB_DM_DN0 I/O A1 USB high-speed differential transceiver (negative)
PWRON0z_BATEN0 I/O, PD B19 USB Port 0 Power On Control for Downstream Power/Battery Charging Enable.
The pin is used for control of the downstream power switch; in addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charger support for the port as indicated in the Battery Charger Support register:
0 = Battery charging not supported
1 = Battery charging supported
This pin provides the port power control for all downstream ports if GANGED_SMBA2 = 1. This pin also determines the battery charging support of all downstream ports if GANGED_SMBA2 = 1.
OVERCUR0z I, PU B21 USB Port 0 overcurrent detection.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
This pin should be pulled high using a 10-kΩ resistor if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power switch.
USB_SSTXP_DN1 O B34 USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1 O A37 USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1 I B33 USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1 I A36 USB SuperSpeed receiver differential pair (negative)
USB_DP_DN1 I/O B36 USB High-speed differential transceiver (positive)
USB_DM_DN1 I/O A39 USB High-speed differential transceiver (negative)
PWRON1z_BATEN1 I/O, PD A21 USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The terminal is used for control of the downstream power switch for Port 1. In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charger support for Port 1 as indicated in the Battery Charger Support register:
0 = Battery Charging Not Supported
1 = Battery Charging Supported
OVERCUR1z I, PU A23 USB Downstream Port 1 Overcurrent Detection.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
This pin should be pulled high using a 10-kΩ resistor if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power management device.
USB_SSTXP_DN2 O B7 USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2 O A8 USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2 I B6 USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2 I A7 USB SuperSpeed receiver differential pair (negative)
USB_DP_DN2 I/O A9 USB High-speed differential transceiver (positive)
USB_DM_DN2 I/O B9 USB High-speed differential transceiver (negative)
PWRON2z_BATEN2 I/O, PD B20 USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 2. In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charger support for Port 2 as indicated in the Battery Charger Support register:
0 = Battery Charging Not Supported
1 = Battery Charging Supported
OVERCUR2z I, PU B22 USB Downstream Port 2 Overcurrent Detection.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
This pin should be pulled high using a 10-kΩ resistor if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power management device.
USB_SSTXP_DN3 O B31 USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3 O A34 USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3 I B30 USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3 I A33 USB SuperSpeed receiver differential pair (negative)
USB_DP_DN3 I/O B29 USB High-speed differential transceiver (positive)
USB_DM_DN3 I/O A31 USB High-speed differential transceiver (negative)
PWRON3z_BATEN3 I/O, PD A22 USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 3. In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charger support for Port 3 as indicated in the Battery Charger Support register:
0 = Battery Charging Not Supported
1 = Battery Charging Supported
OVERCUR3z I, PU A24 USB Downstream Port 3 Overcurrent Detection.
0 = An overcurrent event has occurred
1 = An overcurrent event has not occurred
This pin should be pulled high using a 10K resistor if power management is not implemented. If power management is enabled, the external circuitry needed should be determined by the power management device.
LEDA0z_RMBL0 I, PU B23 USB Port 0 Amber LED Indicator & Device Removable Configuration Bit
1 = Device is Removable
0 = Device is NOT Removable
LEDA1z_RMBL1 I/O, PU B25 USB Port 1 Amber LED Indicator & Device Removable Configuration Bit
1 = Device is Removable
0 = Device is NOT Removable
LEDA2z_RMBL2 I/O, PU B26 USB Port 2 Amber LED Indicator & Device Removable Configuration Bit
1 = Device is Removable
0 = Device is NOT Removable
LEDA3z_RMBL3 I/O, PU B27 USB Port 3 Amber LED Indicator & Device Removable Configuration Bit
1 = Device is Removable
0 = Device is NOT Removable
LEDG0z_USED0 I/O, PU A25 USB Port 0 Green LED Indictor & Port Used Configuration Bit
1 = Port Used
0 = Port is NOT Used
LEDG1z_USED1 I/O, PU A27 USB Port 1 Green LED Indictor & Port Used Configuration Bit
1 = Port Used
0 = Port is NOT Used
LEDG2z_USED2 I/O, PU A28 USB Port 2 Green LED Indictor & Port Used Configuration Bit
1 = Port Used
0 = Port is NOT Used
LEDG3z_USED3 I/O, PU A30 USB Port 3 Green LED Indictor & Port Used Configuration Bit
1 = Port Used
0 = Port is NOT Used
Table 5-5 I2C/SMBUS Signals
SIGNAL NAME TYPE PIN NO. DESCRIPTION
SCL/SMBCLK I/O, PD B17 I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
The SCL_SMBCLK pin is sampled at the deassertion of reset to determine if SuperSpeed USB low power states U1 and U2 are initiated. If SCL_SMBCLK is low, (default), U1 / U2 power states are enabled.
If SCL_SMBCLK is high, entry to U1 / U2 power states is not initiated by the hub downstream ports, but is accepted. This input is over-ridden if SDA_SMBDAT is sampled as a ‘1’. If an EEPROM is installed, U1/U2 power state support is controlled by the Device Configuration Register.
Can be left unconnected if external interface not implemented.
SDA/SMBDAT I/O, PD A19 I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
The SDA_SMBDAT pin is sampled at the deassertion of reset to determine if SuperSpeed USB low power states U1 and U2 are disabled. If SDA_SMBDAT is high, U1 and U2 low power states are disabled. If SDA_SMBDAT is low, U1 and U2 low power states are enabled.
If the optional EEPROM or SMBUS is implemented, the value of the u1u2Disable bit of the Device Configuration Register determines if the low power states U1 and U2 are enabled.
Can be left unconnected if external interface not implemented and U1 and U2 are to be enabled.
SMBUSz I, PU B18 I2C/SMBus mode select.
1 = I2C Mode Selected
0 = SMBus Mode Selected
Can be left unconnected if external interface not implemented.
Table 5-6 Test and Miscellaneous Signals
SIGNAL NAME TYPE PIN NO. DESCRIPTION
JTAG_TCK I/O, PD B13 JTAG test clock. Can be left unconnected.
JTAG_TDI I/O, PU B15 JTAG test data in. Can be left unconnected.
JTAG_TDO I/O, PD A15 JTAG test data out. Can be left unconnected.
JTAG_TMS I/O, PU B14 JTAG test mode select. Can be left unconnected.
JTAG_RSTz I/O, PD A16 JTAG reset. Pull down using an external 1-kΩ resistor for normal operation.
HS_SUSPEND I/O, PD B11 High-speed suspend status output.
0 = High-speed upstream port not suspended
1= High-speed upstream port suspended
The value of the pin is sampled at the deassertion of reset to determine the polarity of the PWRONxz_BATENx pins. If it is sampled as a ‘0’ (default), the polarity is active low. If it is sampled as a ‘1’, the polarity is active high.
Can be left unconnected.
SS_SUSPEND I/O, PD A13 SuperSpeed USB suspend status output.
0 = SuperSpeed USB upstream port not suspended
1= SuperSpeed USB upstream port suspended
The value of the pin is sampled at the deassertion of reset to determine if spread spectrum clocking is enabled or disabled. If it is sampled as a ‘0’ (default), SSC is enabled. If it is sampled as a ‘1’, SSC is disabled.
Can be left unconnected.
HS O, PU A11 High-speed status. The pin is to indicate the connection status of the upstream port as documented below:
0 = Hub in low/full speed mode
1 = Hub in high-speed mode
Can be left unconnected.
SS O, PU A12 SuperSpeed USB status. The pin is to indicate the connection status of the upstream port as documented below:
0 = Hub not in SuperSpeed USB mode
1 = Hub in SuperSpeed USB mode
Can be left unconnected.
FULLPWRMGMTz_
SMBA1		 I, PU A17 Full power management enable/SMBus address bit 1.
The value of the pin is sampled at the de-assertion of reset to set the power switch control follows:
0 = Full power management supported
1 = Full Power management not supported
Full power management is the ability to control power to the downstream ports of the TUSB8040A1 using the PWRON0z_BATEN0 terminal. When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus target address bit 1. SMBus target address bits 2 and 3 are always 1 for the TUSB8040A1. When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus target address bit 1.
Can be left unconnected if full power management and SMBus are not implemented.
GANGED_SMBA2 I, PU A41 Ganged operation enable/SMBus Address bit 2.
The value of the pin is sampled at the deassertion of reset to set the power switch and over current detection mode as follows:
0 = Power Gangs not supported
1 = Power Gangs supported
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus target address bit 2.
PORTINDz_SMBA3 I, PU B37 Port Indicator LED Status/SMBus Address bit 3.
The value of the pin is sampled at the deassertion of reset to determine the port indicator support for the hub as follows:
0 = Port Indicator LEDs are enabled
1 = Port Indicator LEDs are not enabled
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus target address bit 3.
Table 5-7 Power Signals
SIGNAL NAME TYPE PIN NO. DESCRIPTION
VDD33 P B2, A10,
A14, B24,
B28, B35,
A45, A47,
B46, B48		 3.3-V power rail
VDD P A2, A5,
A6, B8,
B10, B12,
B16, A20,
A26, A29,
A32, A35,
A38, B38,
B41, B43,
A52		 1.1-V power rail
GND G A43, A53 Ground, Power Pad
GND_NC G C1, C2,
C3, C4		 The corner pins, which are for mechanical stability of the package, are connected to ground internally. These pins may be connected to GND or left unconnected.
NC NC A40, A51,
B5, B32,		 No connect