JAJSD85A June   2017  – August 2017 TUSB8043

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics, 3.3-V I/O
    6. 7.6 Timing Requirements, Power-Up
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 I2C Programming Support Using Internal Hid to I2C Interface
        1. 8.3.3.1 SET REPORT (Output)
        2. 8.3.3.2 GET REPORT (Feature)
        3. 8.3.3.3 GET REPORT (Input)
      4. 8.3.4 One Time Programmable (OTP) Configuration
      5. 8.3.5 Clock Generation
      6. 8.3.6 Crystal Requirements
      7. 8.3.7 Input Clock Requirements
      8. 8.3.8 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
      22. 8.5.22 Manufacturer String Registers
      23. 8.5.23 Product String Registers
      24. 8.5.24 Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8043 Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8043 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGC|64
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGC Package
64 Pin (VQFN)
(Top View)
TUSB8043 po_rgc_sllset2.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
Clock and Reset Signals
GRSTz 50 I
PU		 Global power reset. This reset brings all of the TUSB8043 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
XI 62 I Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
XO 61 O Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between XI and XO.
USB Upstream Signals
USB_SSTXP_UP 55 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_UP 56 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_UP 58 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_UP 59 I USB SuperSpeed receiver differential pair (negative)
USB_DP_UP 53 I/O USB High-speed differential transceiver (positive)
USB_DM_UP 54 I/O USB High-speed differential transceiver (negative)
USB_R1 64 I Precision resistor reference. A 9.53-kΩ ±1% resistor should be connected between USB_R1 and GND.
USB_VBUS 48 I USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-KΩ ±1% resistor, and to ground through a 10-kΩ ±1% resistor from the signal to ground.
USB Downstream Signals
USB_SSTXP_DN1 3 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN1 4 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN1 6 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN1 7 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN1 1 I/O USB High-speed differential transceiver (positive)
USB_DM_DN1 2 I/O USB High-speed differential transceiver (negative)
PWRCTL1/BATEN1 36 I/O, PD USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 1. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR1z 46 I, PU USB Port 1 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 1.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN2 11 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN2 12 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN2 14 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN2 15 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN2 9 I/O USB High-speed differential transceiver (positive)
USB_DM_DN2 10 I/O USB High-speed differential transceiver (negative)
PWRCTL2/BATEN2 35 I/O, PD USB Port 2 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 2. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 2 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR2z 47 I, PU USB Port 2 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 2.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN3 19 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN3 20 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN3 22 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN3 23 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN3 17 I/O USB High-speed differential transceiver (positive)
USB_DM_DN3 18 I/O USB High-speed differential transceiver (negative)
PWRCTL3/BATEN3 33 I/O, PD USB Port 3 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 3. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 3 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR3z 44 I, PU USB Port 3 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 3.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
USB_SSTXP_DN4 26 O USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM_DN4 27 O USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP_DN4 29 I USB SuperSpeed receiver differential pair (positive)
USB_SSRXM_DN4 30 I USB SuperSpeed receiver differential pair (negative)
USB_DP_DN4 24 I/O USB High-speed differential transceiver (positive)
USB_DM_DN4 25 I/O USB High-speed differential transceiver (negative)
PWRCTL4/BATEN4 32 I/O, PD USB Port 4 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 4. This pin be left unconnected if power management is not implemented.
In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 4 as indicated in the Battery Charging Support register:
0 = Battery charging not supported
1 = Battery charging supported
OVERCUR4z 43 I, PU USB Port 4 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 4.
0 = An over current event has occurred
1 = An over current event has not occurred
When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected.
I2C/SMBUS I2C Signals
SCL/SMBCLK 38 I/O, PD I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SDA/SMBDAT 37 I/O, PD I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.
Can be left unconnected if external interface not implemented.
SMBUSz/SS_SUSPEND 39 I/O, PU I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled at the de-assertion of reset set I2C or SMBus mode as follows:
1 = I2C Mode Selected
0 = SMBus Mode Selected
Can be left unconnected if external interface not implemented.
After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended.
Test and Miscellaneous Signals
FULLPWRMGMTz / FULLAUTOz / SMBA1/SS_UP 40 I/O, PD Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status Upstream port.
The value of the pin is sampled at the de-assertion of reset to set the power switch control follows:
0 = Power switching and over current inputs supported
1 = Power switching and over current inputs not supported
Full power management is the ability to control power to the downstream ports of the TUSB8043 using PWRCTL[4:1]/BATEN[4:1].
If BATENx = 1 on any port, full power management must be enabled so the value of the terminal is sampled at the de-assertion to initialize the value of the FULLAUTOz bit.
When AUTOENz = 0 and FULLAUTOz = 0: all ACP modes are supported.
When AUTOENz = 0 and FULLAUTOz = 1:only highest current ACP mode is used in auto mode.
When SMBus mode is enabled, this pin sets the value of the SMBus slave address bit 1.
Can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal indicates the SuperSpeed USB connection status of the upstream port if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable port.
Note: Power switching must be supported for battery charging applications.
PWRCTL_POL 41 I/O, PU Power Control Polarity.
The value of the pin is sampled at the de-assertion of reset to set the polarity of PWRCTL[4:1].
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
GANGED/SMBA2/
HS_UP		 42 I/O, PD Ganged operation enable/SMBus Address bit 2/HS Connection Status Upstream Port.
The value of the pin is sampled at the de-assertion of reset to set the power switch and over current detection mode as follows:
0 = Individual power control supported when power switching is enabled
1 = Power control gangs supported when power switching is enabled
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 2.
After reset, this signal indicates the High-speed USB connection status of the upstream port if enabled through the stsOutputEn bit in Additional Feature Configuration register. When enabled, a value of 1 indicates the upstream port is connected to a High-speed USB capable port.
Note: Individual power control must be enabled for battery charging applications.
AUTOENz/
HS_SUSPEND		 45 I/O, PU Automatic Charge Mode Enable/HS Suspend Status.
The value of the pin is sampled at the de-assertion of reset to determine if automatic mode is enabled as follows:
0 = Automatic Mode is enabled on ports that are enabled for battery charging when the hub is unconnected. Please note that CDP is not supported on Port 1 when operating in Automatic mode.
1 = Automatic Mode is disabled
This value is also used to set the autoEnz bit in the Battery Charging Support Register.
After reset, this signal indicates the High-speed USB Suspend status of the upstream port if enabled through the stsOutputEn bit in Additional Feature Configuration register. When enabled, a value of 1 indicates the connection is suspended.
TEST 49 I, PD This pin is reserved for factory test. It is suggested to have this pin pulled down to ground on PCB.
Power and Ground Signals
VDD 5, 8,
13, 21,
28, 31,
51, 57 		PWR 1.1-V power rail
VDD33 16, 34,
52, 63 		PWR 3.3-V power rail
VSS (Thermal Pad) PWR Ground. Thermal pad must be connected to ground.
NC 60 — No connect, leave floating