JAJSD85A June   2017  – August 2017 TUSB8043

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics, 3.3-V I/O
    6. 7.6 Timing Requirements, Power-Up
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 I2C Programming Support Using Internal Hid to I2C Interface
        1. 8.3.3.1 SET REPORT (Output)
        2. 8.3.3.2 GET REPORT (Feature)
        3. 8.3.3.3 GET REPORT (Input)
      4. 8.3.4 One Time Programmable (OTP) Configuration
      5. 8.3.5 Clock Generation
      6. 8.3.6 Crystal Requirements
      7. 8.3.7 Input Clock Requirements
      8. 8.3.8 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 Port Configuration
      4. 8.4.4 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Registers
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Device Configuration Register 3
      20. 8.5.20 USB 2.0 Only Port Register
      21. 8.5.21 Serial Number String Registers
      22. 8.5.22 Manufacturer String Registers
      23. 8.5.23 Product String Registers
      24. 8.5.24 Additional Feature Configuration Register
      25. 8.5.25 SMBus Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Discrete USB Hub Product
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Upstream Port Implementation
          2. 9.2.1.2.2 Downstream Port 1 Implementation
          3. 9.2.1.2.3 Downstream Port 2 Implementation
          4. 9.2.1.2.4 Downstream Port 3 Implementation
          5. 9.2.1.2.5 Downstream Port 4 Implementation
          6. 9.2.1.2.6 VBUS Power Switch Implementation
          7. 9.2.1.2.7 Clock, Reset, and Misc
          8. 9.2.1.2.8 TUSB8043 Power Implementation
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB8043 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Examples
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGC|64
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage Range VDD Steady-state supply voltage –0.3 1.4 V
VDD33 Steady-state supply voltage –0.3 3.8 V
Voltage Range USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals -0.3 1.4 V
XI terminals -0.3 2.45 V
All other terminals -0.3 3.8 V
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD(1) 1.1V supply voltage 0.99 1.1 1.26 V
VDD33 3.3V supply voltage 3 3.3 3.6 V
USB_VBUS Voltage at USB_VBUS PAD 0 1.155 V
TA Operating free-air temperature TUSB8043 0 70 °C
TJ Operating junction temperature –40 105 °C
(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

THERMAL METRIC(1) TUSB8043 UNIT
RGC
64 PINS
RθJA Junction-to-ambient thermal resistance 26 °C/W
RθJCtop Junction-to-case (top) thermal resistance 11.5 °C/W
RθJB Junction-to-board thermal resistance 5.3 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.2 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 1.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)
PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage(1) VDD33 2 VDD33 V
VIL Low-level input voltage(1) VDD33 0 0.8 V
VI Input voltage 0 VDD33 V
VO Output voltage(2) 0 VDD33 V
tt Input transition time (trise and tfall) 0 25 ns
Vhys Input hysteresis(3) 0.13 x VDD33 V
VOH High-level output voltage VDD33 IOH = -4 mA 2.4 V
VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V
IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA
IOZP High-impedance, output current with internal pullup or pulldown resistor(4) VDD33 VI = 0 to VDD33 ±250 µA
II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA
RPD Internal pull-down resister 13.5 19 27.5 KΩ
RPU Internal pull-up resistor 14.5 19 25 KΩ
(1) Applies to external inputs and bidirectional buffers.
(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pullups/pulldowns.
(5) Applies to external input buffers.

7.6 Timing Requirements, Power-Up

PARAMETER DESCRIPTION MIN TYP MAX UNIT
td1 VDD33 stable before VDD stable(3) See (2) ms
td2 VDD and VDD33 stable before de-assertion of GRSTz 3 ms
tsu_io Setup for MISC inputs(1) sampled at the de-assertion of GRSTz 0.1 µs
thd_io Hold for MISC inputs(1) sampled at the de-assertion of GRSTz 0.1 µs
tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms
tVDD_RAMP VDD supply ramp requirements 0.2 100 ms
(1) MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL.
(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 µs before the VDD33.
(3) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.
TUSB8043 pwr_up_timing_sllsee4.gif Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at TA = 25°C
PARAMETER VDD33 VDD UNIT
3.3 V 1.1 V
LOW POWER MODES
Power On (after Reset)                    3 30 mA
Upstream Disconnect 3 24 mA
Suspend                                   3 30 mA
ACTIVE MODES (US state / DS State)
3.0 host / 1 SS Device and Hub in U1 / U2 45 240 mA
3.0 host / 1 SS Device and Hub in U0 45 356 mA
3.0 host / 2 SS Devices and Hub in U1 / U2 45 301 mA
3.0 host / 2 SS Devices and Hub in U0 45 457 mA
3.0 host / 3 SS Devices and Hub in U1 / U2 45 372 mA
3.0 host / 3 SS Devices and Hub in U0 45 563 mA
3.0 host / 4 SS Devices and Hub in U1 / U2 45 440 mA
3.0 host / 4 SS Devices and Hub in U0 45 672 mA
3.0 host / 1 SS Device in U0 and 1 HS Device 84 372 mA
3.0 host / 2 SS Devices in U0 and 2 HS Devices 95 512 mA
2.0 host / HS Device 45 55 mA
2.0 host / 4 HS Devices 76 74 mA