JAJSCQ9A December   2016  – February 2019 UC1843A-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 UVLO
      2. 8.3.2 Reference
      3. 8.3.3 Totem-Pole Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Oscillator
        2. 9.2.2.2 Current Sensing and Limiting
        3. 9.2.2.3 Error Amplifier
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Input/Output Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.3 Error Amplifier

The error amplifier (E/A) configuration is shown in Figure 19. The non-inverting input is not brought out to a pin, but is internally biased to 5 V ±2%. The E/A output is available at pin 1 for external compensation, allowing the user to control the converter’s closed-loop frequency response.

Figure 20 shows an E/A compensation circuit suitable for stabilizing any current-mode controlled topology except for flyback and boost converters operating with inductor current. The feedback components add a pole to the loop transfer function at ƒp = ½ π RF. RF and CF are chosen so that this pole cancels the zero of the output filter capacitor ESR in the power circuit. RI and RF fix the low-frequency gain. They are chosen to provide as much gain as possible while still allowing the pole formed by the output filter capacitor and load to roll off the loop gain to unity (0 dB) at ƒ ≈ ƒSWITCHING / 4. This technique ensures converter stability while providing good dynamic response.

UC1843A-SP EA_config_LUSC14.gifFigure 19. E/A Configuration
UC1843A-SP compensation_LUSC14.gifFigure 20. Compensation

The E/A output sources 0.5 mA and sinks 2 mA. A lower limit for RF is given by:

Equation 6. UC1843A-SP eq_06_LUSC14.gif

E/A input bias current (2-µA max) flows through RI, resulting in a DC error in output voltage (VO) given by:

Equation 7. UC1843A-SP eq_07_LUSC14.gif

Therefore, the designer should keep the value of RI, as low as possible.

Figure 21 shows the open-loop frequency response of the UC1843A-SP E/A. The gain represents an upper limit on the gain of the compensated E/A. Phase lag increases rapidly as frequency exceeds 1 MHz due to second-order poles at about 10 MHz and above.

Continuous-inductor-current boost and flyback converters each have a right-half-plane zero in their transfer function. An additional compensation pole is needed to roll off loop gain at a frequency less than that of the RHP zero. RP and CP in the circuit of Figure 14 provide this pole.

UC1843A-SP V_gain_vs_f_LUSC14.gifFigure 21. Error Amplifier Open-Loop Frequency Response