SLUS871D January   2009  – December 2016 UC1846-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference
      2. 7.3.2  Oscillator
      3. 7.3.3  Slope Compensation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Current Sense Amplifier
      6. 7.3.6  Current Limit
      7. 7.3.7  Shutdown
      8. 7.3.8  Output Section
      9. 7.3.9  Undervoltage Lockout
      10. 7.3.10 Soft-Start
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 8 V (Minimum VIN)
      2. 7.4.2 Synchronization
      3. 7.4.3 Parallel Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscillator Circuit Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor Selection
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Output Inductor Selection
          4. 8.2.1.2.4 Switching Frequency
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Parallel Operation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Soft-Start and Shutdown/Restart Functions Application
      4. 8.2.4 Open-Loop Test Circuit Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The UC1846-SP control devices provide all of the necessary features to implement fixed frequency, current mode control schemes while maintaining a minimum external parts count. The superior performance of this technique can be measured in improved line regulation, enhanced load response characteristics, and a simpler, easier-to-design control loop. Topological advantages include inherent pulse-by-pulse current limiting capability, automatic symmetry correction for push-pull converters, and the ability to parallel “power modules" while maintaining equal current sharing.

7.2 Functional Block Diagram

UC1846-SP block_dgm_lus871.gif

NOTE:

Pin numbers shown are for the J package.

7.3 Feature Description

UC1846-SP is a current mode controller, used to support various topologies such as forward, flyback, half-bridge, full bridge, push-pull configurations.

Current mode control is a two-loop system. The switching power supply inductor is hidden within the inner current control loop. This simplifies the design of the outer voltage control loop and improves power supply performance in many ways, including better dynamics. The objective of this inner loop is to control the state-space averaged inductor current, but in practice the instantaneous peak inductor current is the basis for control (switch current, equal to inductor current during the on time, is often sensed). If the inductor ripple current is small, peak inductor current control is nearly equivalent to average inductor current control.

The peak method of inductor current control functions by comparing the upslope of inductor current (or switch current) to a current program level set by the outer loop. The comparator turns the power switch off when the instantaneous current reaches the desired level. The current ramp is usually quite small compared to the programming level, especially when VIN is low. As a result, this method is extremely susceptible to noise. A noise spike is generated each time the switch turns on. A fraction of a volt coupled into the control circuit can cause it to turn off immediately, resulting in a sub-harmonic operating mode with much greater ripple. Circuit layout and bypassing are critically important to successful operation.

The peak current mode control method is inherently unstable at duty ratios exceeding 0.5, resulting in sub-harmonic oscillation. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. A slope compensation must be added to the sensed current waveform or subtracted from the control voltage to ensure stability above a 50% duty cycle. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability.

The pulse width modulator (PWM) of UC1846-SP is limited to a maximum duty cycle of 50%, thus it can be used in topologies such as push-pull, half bridge, full bridge, forward, flyback configurations. Limiting PWM to 50% duty cycle ensures that for isolated or transformer based topologies. The transformer is allowed to reset and prevent saturation of the transformer core.

Pulse-by-pulse symmetry correction (flux balancing) is inherent to current mode controllers and essential for the push-pull topology to prevent core saturation.

Current limit control design has numerous advantages:

  1. Current mode control provided peak switch current limiting – pulse by pulse current limit.
  2. Control loop is simplified as one pole due to output inductor is pushed to higher frequency , thus a two pole system turns into two real poles. Thus system reduces to a first order system thus simplifies the control.
  3. Multiple converter can be paralleled and allows equal current sharing amount the various converters.
  4. Inherently provides for input voltage feed-forward as any perturbation in the input voltage will be reflected in the switch or inductor current. Since switch or inductor current is a direct control input, thus this perturbation is very rapidly corrected.
  5. The error amplifier output (outer control loop) defines the level at which the primary current (inner loop) will regulate the pulse width, and output voltage.

UC1846-SP push_pull_converter_using_slusbv6.gif Figure 3. Push-Pull Converter Using Current Mode Control

7.3.1 Reference

As highlighted in the Functional Block Diagram, UC1846-SP incorporates a 5.1-V internal reference regulator with ±10% set point variation over temperature.

7.3.2 Oscillator

Figure 8 highlights the oscillator circuit. Connecting a resistor RT from pin 9 to ground establishes a current, which is mirrored to pin 8 and charges the capacitor connected from pin 8 to ground. Maximum on time corresponds to the maximum charging time of the timing capacitor. Oscillator frequency can be determined by .

Off-time corresponds to capacitor discharge time establishes the converter dead time between the pulses according to . Internal 8-mA current sink discharges the CT pin capacitor.

7.3.3 Slope Compensation

For duty cycle above 50% slope compensating can be implemented by using a buffer (that is, 2N2222) and connecting base to timing capacitor pin 8, collector to VREF (5 V), a resistor in series with emitter connected to (pin 4) CS+ of differential current sense amplifier. Injecting a downslope proportional to the sawtooth into current sense amplifier.

As with any bipolar PWM IC, outputs should be protected from negatively biasing the substrate. This is typically done by using Schottky diodes from ground to each output. Failure to do this could cause spurious interruption and restart of the oscillator, dropping of output pulses and a significant increase in propagation delays.

7.3.4 Error Amplifier

UC1846-SP incorporates an error amplifier with typical open loop gain of 100 dB and gain bandwidth of 1.5 MHz. With Source and sink capability of 10 mA and 0.5 mA respectively.

UC1846-SP err_amp_out_con_SLUS227.gif
Error amplifier sources up to 0.5 mA.
Figure 4. Error Amplifier Output Configuration

7.3.5 Current Sense Amplifier

UC1846-SP incorporates a differential current sense amplifier which can eliminate ground loop problems and increase noise immunity. An R-C snubber can also be implemented thus helping in blanking the peak current spike when the switch is turned on. The input of the current sense amplifier is slew rate limited allowing lower values of filter capacitors to be used to eliminate leading edge noise.

UC1846-SP cur_sen_amp_con_SLUS227.gif
A small RC filter may be required in some applications to reduce switch transients. Differential input allows remote, noise-free sensing.
Figure 5. Current-Sense Amplifier Connections

In some applications, a small RC filter is required to reduce switch transients. Differential input allows remote noise sensing.

7.3.6 Current Limit

Over current trip point is determined by Equation 1. Differential current sense amplifier has a gain of three, as shown in Figure 6.

UC1846-SP pul_by_pul_cur_lim_slusbv6.gif Figure 6. Pulse-By-Pulse Current Limiting

Referring to Figure 6, Equation 1 determines the peak current, Is.

Equation 1. UC1846-SP q4_pulse_current_slus227.gif

7.3.7 Shutdown

UC1846-SP incorporates a shutdown pin (pin 16). Shutdown threshold voltage is 350 mV. Exceeding the shutdown threshold voltage causes the device to shutdown.

  • If current into ICL_SS VREF/R1 > 3-mA SCR holding current (minimum latch current), then the device latches off. Power recycle is required to un-latch the device.
  • If VREF/R1 < 0.8 mA, that is ICL_SS < 0.8 A, then this ensures that the circuit does not latch in a shutdown state.
UC1846-SP app_inf_slus871.gif Figure 7. Shutdown Latch

Referring to Figure 11, if

Equation 2. UC1846-SP q5_sd_with_slus227.gif

the shutdown latch commutates when ISS = 0.8 mA and a restart cycle initiates.

Referring to Figure 12, if

Equation 3. UC1846-SP q6_sd_without_slus227.gif

the device latches off until power is recycled.

7.3.8 Output Section

UC1846-SP incorporates high current dual totem pole output stage capable of sourcing/sinking 1.5-A peak current for fast switching of power MOSFETs and limited to 0.5-A DC current.

7.3.9 Undervoltage Lockout

Minimum input voltage for converter is 8 V or higher, with typical value being 7.7 V. At input voltages below the actual UVLO voltage, the devices will not operate.

7.3.10 Soft-Start

Connecting a capacitor from CL/SS pin 1 to ground which is charged by 0.5-mA internal current source will determine the soft-start time. If over current is also implemented as shown in Figure 6, then SS charge time will be determined by charging SS capacitor by 0.5-mA current as well as current contributed by R1 resistor in charging the SS capacitor.

7.4 Device Functional Modes

7.4.1 Operation With VIN < 8 V (Minimum VIN)

The devices operate with input voltages above 8 V. The maximum UVLO voltage is 8 V and will operate at input voltages above 8 V. The typical UVLO voltage is 7.7 V and the devices may operate at input voltages above that point. The devices also may operate at lower input voltages, the minimum UVLO voltage is not specified. At input voltages below the actual UVLO voltage, the devices will not operate.

7.4.2 Synchronization

The synchronization pin (pin10) can be configured as an output for master/slave application. When the converter is configured as a master or standalone converter, SYNC (pin 10) is an output. As highlighted in the functional block diagram, voltage at RT (pin 9) is greater than 4.1-V internal threshold.

When using the part in slave configuration, SYNC pin becomes an input. Typical example of parallel operation with master/slave configuration is shown in Figure 13. Slave unit CT (pin 8) is grounded and RT pin is connected to VREF (pin 2).

When using the part in slave configuration, SYNC pin becomes an input. Typical example of parallel operation with master/slave configuration is shown in Figure 13. Slave unit CT (pin 8) is grounded and RT pin is connected to VREF (pin 2). Under parallel configuration two or more units can be paralleled, with COMP pins tied together each will share current equally.

7.4.3 Parallel Operation

Under parallel configuration two or more units can be paralleled, with COMP pins tied together each will share current equally.

Figure 13 highlights typical parallel operation configuration.