JAJSMY4C September   2021  – December 2022 UCC14240-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety Limiting Values
    10. 6.10 Insulation Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Overvoltage Protection
        4. 7.3.4.4 Overpower Protection
          1. 7.3.4.4.1 Output Undervoltage Protection
        5. 7.3.4.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 RLIM Resistor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pins 6 to 7 (VIN) and pins 8 to 9 (GNDP). For the isolated output supply, (VDD – VEE), place the capacitors between pins 28 to 29 (VDD) and pins 30 to 31 (VEE). For the isolated output supply, (COM – VEE), place an RLIM resistor between the RLIM pin and the gate driver COM supply input. Also place decoupling capacitors at the gate driver supply pins (COM and VEE) and at gate driver supply pins (VDD and VEE) with values according to the following component calculation sections. These locations are of particular importance to all the decoupling capacitors because the capacitors supply the transient current associated with the fast switching waveforms of the power drive circuits. Ensure the capacitor dielectric material is compatible with the target application temperature.