JAJSQ36A april   2023  – august 2023 UCC14241-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Insulation Specifications
    6. 7.6 Electrical Characteristics
    7. 7.7 Safety Limiting Values
  9. Safety-Related Certifications
  10. Insulation Characteristics
  11. 10Typical Characteristics
  12. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1 Power Stage Operation
        1. 11.3.1.1 VDD-VEE Voltage Regulation
        2. 11.3.1.2 COM-VEE Voltage Regulation
        3. 11.3.1.3 Power Handling Capability
      2. 11.3.2 Output Voltage Soft Start
      3. 11.3.3 ENA and PG
      4. 11.3.4 Protection Functions
        1. 11.3.4.1 Input Undervoltage Lockout
        2. 11.3.4.2 Input Overvoltage Lockout
        3. 11.3.4.3 Output Undervoltage Protection
        4. 11.3.4.4 Output Overvoltage Protection
        5. 11.3.4.5 Overpower Protection
        6. 11.3.4.6 Overtemperature Protection
    4. 11.4 Device Functional Modes
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1 Capacitor Selection
        2. 12.2.2.2 Single RLIM Resistor Selection
        3. 12.2.2.3 RDR Circuit Component Selection
        4. 12.2.2.4 Feedback Resistors Selection
      3. 12.2.3 Application Curves
    3. 12.3 System Examples
    4. 12.4 Power Supply Recommendations
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information
  16. 15Tape and Reel Information

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メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Single RLIM Resistor Selection

The UCC14241-Q1 device creates an isolated output VDD-VEE as its main output. It also creates a second output COM-VEE, using VDD-VEE as its power source. Because both outputs are isolated from the input, and sharing VEE as the common reference point, the UCC14241-Q1 outputs can be configured as dual-output two-positive, dual-output two-negative, or dual-output one-positive and one-negative, as shown in Figure 12-6.

GUID-52BF06CA-D1A2-46BA-BCBC-7B23D8A4CEB9-low.svg GUID-1E059162-036F-4804-B1B9-73B7AAD35F92-low.svg
(a) Dual-output, two-positive (b) Dual-output, two-negative
GUID-4A54142E-05B9-4338-844F-55F4DC90293A-low.svg
(c) Dual-output, one-positive, one-negative

Figure 12-6 Dual output configurations

When the module is configured as dual-positive or dual-negative outputs, the RLIM resistor is a true current limiting resistor. Set up the RLIM resistor value as the maximum load current needed for VOUT2, using Equation 15. IVOUT2_max is the maximum load current for VOUT2 output.

Equation 9. R L I M = V O U T 2 I V O U T 2 _ m a x   - R L I M _ I N T

RLIM_INT is the internal switch resistance value of 30 Ω typical.

For isolated gate driver applications, one positive and one negative outputs are needed. In this case, VDD-VEE is the total output voltage, and the middle point becomes the reference point. Because the total voltage between VDD and VEE is always regulated through the FBVDD feedback, the RLIM pin only must regulate the middle point voltage so that it can give the correct positive and negative voltages. The RLIM control is achieved through FBVEE pin as described in COM-VEE Voltage Regulation.

Based on UCC14241-Q1 車載用 2W、24V VIN25V VOUT、高密度、
5kVRMS 超、絶縁型 DC/DC モジュールPower Stage OperationOutput Voltage Soft Start ENA and PG Capacitor SelectionSingle RLIM Resistor SelectionRDR Circuit Component SelectionFeedback Resistors Selection
, when selecting the output capacitor ratio proportional to the voltage ratio, the capacitors form a voltage divider. The middle point voltage must naturally give the correct positive and negative voltages. At the same time, for the gate driver circuit, the gate charge pulled out from the positive rail capacitor during turn-on is fed back to the negative rail capacitor during turn-off, the two output rail load must always be balanced. However, due to the gate driver circuit quiescent current unbalancing, and the two-rail capacitance tolerances, the middle point voltage can move away with time. The RLIM pin provides an opposite current to keep the middle point voltage at the correct level.

As illustrated in Figure 12-7 (a), without considering the gate charge, the gate driver circuit quiescent current loads the positive rail and negative rail differently. The net current shows up as a DC offset current to the middle point.

As illustrated in Figure 12-7 (b), every time the gate driver circuit turns-on the main power switch, it pulls the charge out of the positive and negative rail output capacitors. When the module power stage provides energy to the secondary side, refreshing those capacitors, the same charge is fed into both capacitors. If the capacitor values are perfect, the voltage rise in the capacitors will be proportional. The positive and negative voltages would not change. However, due to the capacitor tolerances, the capacitor values are not perfectly matched. The voltages will rise at different ratios with the smaller capacitor rising faster. Over time, the middle point voltage, COM, would pull to a different value. A load across one of the capacitors will pull towards a voltage imbalance. The RLIM function counteract the voltage imbalance and bring the COM voltage back into regulation.

GUID-0F8AD383-24D8-4049-BBA1-1A66A252A503-low.svg GUID-11EB39CF-8637-4DEC-939A-096E2E64EDC0-low.svg
(a) Load current unbalancing (b) Capacitance unbalancing

Figure 12-7 Source of voltage unbalancing
Considering these two effects, the RLIM must provide enough current to compensate this offset current. The RLIM must be low enough to provide enough current, but not too low otherwise the middle point voltage is corrected at each turn on and turn off edge of the gate driver and excessive power loss is generated.

The RLIM resistor is chosen to provide enough current for the load using the following 3 equations, whichever has lowest value.

Equation 10. R L I M _ M A X _ H = V V D D - C O M C O U T 3 × 1 - C O U T 3 C O U T 2 × 1 - C O U T 2 + C O U T 3 × 1 - C O U T 3 - C O U T 3 C O U T 2 + C O U T 3 × Q G _ T o t a l × f S W + I C O M _ S O U R C E - R L I M _ I N T
where
  • QG_Total is the total gate charge of power switch.
  • fSW is the switching frequency of gate drive load.
  • ∆ICOM_SOURCE=ICOM-VEE-IVDD-COM, when ICOM-VEE>IVDD-COM. Otherwise, ∆ICOM_SOURCE=0A.

Equation 11. R L I M _ M A X _ L 1 = V C O M - V E E C O U T 2 × 1 - C O U T 2 C O U T 2 × 1 - C O U T 2 + C O U T 3 × 1 - C O U T 3 - C O U T 2 C O U T 2 + C O U T 3 × Q G _ T o t a l × f S W + I C O M _ S I N K - R L I M _ I N T

where ∆ICOM_SINK=IVDD-COM-ICOM-VEE, when ICOM-VEE<IVDD-COM. Otherwise, ∆ICOM_SINK=0A.

Equation 12. R L I M _ M A X _ L 2 = V C O M - V E E C O U T 3 + T O L E R A N C E C O U T 3 × 0.10 × V C O M - V E E 3   m s + I C O M _ S I N K - R L I M _ I N T
Select RLIM value to be the lowest of either 1) the RLIM needed for capacitor imbalance and the load, calcualted by RLIM_MAX_H and RLIM_MAX_L1, or 2) the RLIM needed to respond to a VCOM-VEE transient within 3 ms with the given load current, calcuated by RLIM_MAX_L2.

RLIM value determines response time of (COM – VEE) regulation. Too low an RLIM value can cause oscillation and can overload (VDD – VEE). Too high an RLIM value can give offset errors, due to slow response. If RLIM is greater than above calculations, then there is not enough current available to replenish the charge to the output capacitors, causing a charge imbalance where the voltage is not able to maintain regulation, and eventually exceeds the OVP or UVP FAULT thresholds and shutting down the device for protection. Choose RLIM value to be close but smaller than the smallest value of the three calculated results.

The power loss of RLIM can be derived as

Equation 13. P R L I M = V V D D - C O M 2 R L I M D u t y R L I M + ( C O U T 2 × 1 - C O U T 2 C O U T 2 × 1 - C O U T 2 + C O U T 3 × 1 - C O U T 3 - C O U T 2 C O U T 2 + C O U T 3 × Q G _ T o t a l × f S W + I C O M _ S I N K ) 2 × R L I M
where DutyRLIM is the duty cycle of RLIM-pin switch on-time respect to the switching cycle. 33% can be used as a reasonable rule of thumb for power loss calculation purpose.