JAJS124Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select Rectifier Diodes
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
          1. 8.2.2.10.1 Output Voltage Setpoint
          2. 8.2.2.10.2 Voltage Loop Compensation
          3. 8.2.2.10.3 Setting the Switching Frequency
          4. 8.2.2.10.4 Soft Start
          5. 8.2.2.10.5 Setting the Switching Delays
          6. 8.2.2.10.6 Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
      2. 11.1.2 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to 85°C for UCC2895x and TA = –55°C to 125°C for the UCC1895x (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO(on) Start-up voltage threshold 10.2 11 11.8 V
UVLO(off) Minimum operating voltage after start-up 8.2 9 9.8 V
UVLO(hys) Hysteresis 1 2 3 V
SUPPLY
ISTART Start-up current VDD = 8 V 150 250 µA
IDD Operating current 5 6 mA
VDD_CLAMP VDD clamp voltage IDD = 10 mA 16.5 17.5 18.5 V
VOLTAGE REFERENCE
VREF Output voltage TJ = 25°C 4.94 5 5.06 V
10 V < VDD < VDD_CLAMP,
0 mA < IREF < 5 mA,
temperature		 4.85 5 5.15
ISC Short circuit current REF = 0 V, TJ = 25°C 10 20 mA
ERROR AMPLIFIER
Common-mode input voltage range –0.1 3.6 V
VIO Offset voltage –7 7 mV
IBIAS Input bias current (EAP, EAN) –1 1 µA
EAOUT_VOH High-level output voltage EAP – EAN = 500 mV, IEAOUT = –0.5 mA 4 4.5 5 V
EAOUT_VOL Low-level output voltage EAP – EAN = –500 mV, IEAOUT = 0.5 mA 0 0.2 0.4 V
ISOURCE Error amplifier output source current EAP – EAN = 500 mV, EAOUT = 2.5 V 1 1.5 mA
ISINK Error amplifier output sink current EAP – EAN = –500 mV, EAOUT = 2.5 V 2.5 4.5 mA
AVOL Open-loop dc gain 75 85 dB
GBW Unity gain bandwidth(1) 5 7 mHz
Slew rate(1) 1 V < EAN < 0 V, EAP = 500 mV,
0.5 V < EAOUT < 3 V		 1.5 2.2 V/µs
No-load comparator turn-off threshold 0.45 0.5 0.55 V
No-load comparator turn-on threshold 0.55 0.6 0.69 V
No-load comparator hysteresis 0.035 0.1 0.165 V
OSCILLATOR
fOSC Frequency TJ = 25°C 473 500 527 kHz
Frequency total variation Over line, temperature 2.5% 5%
VIH_SYNC SYNC input threshold, SYNC 2.05 2.1 2.4 V
VOH_SYNC High-level output voltage, SYNC ISYNC = –400 μA, VCT = 2.6 V 4.1 4.5 5 V
VOL_SYNC Low-level output voltage, SYNC ISYNC = 100 μA, VCT = 0 V 0 0.5 1 V
Sync output pulse width LOADSYNC = 3.9 kΩ and 30 pF in parallel 85 135 ns
VRT Timing resistor voltage 2.9 3 3.1 V
VCT(peak) Timing capacitor peak voltage 2.25 2.35 2.55 V
VCT(valley) Timing capacitor valley voltage 0 0.2 0.4 V
CURRENT SENSE
ICS(bias) Current sense bias current 0 V < CS < 2.5 V,
0 V ADS < 2.5 V		 –4.5 20 µA
Peak current threshold 1.9 2 2.1 V
Overcurrent threshold 2.4 2.5 2.6 V
Current sense to output delay 0 V ≤ CS ≤ 2.3 V,
DELAB = DELCD = REF		 75 110 ns
SOFT START/SHUTDOWN
ISOURCE Soft-start source current SS/DISB = 3.0 V,
CS = 1.9 V		 –40 –35 –30 µA
ISINK Soft-start sink current SS/DISB = 3.0 V,
CS = 2.6 V		 325 350 375 µA
Soft-start/disable comparator threshold 0.44 0.5 0.56 V
ADAPTIVE DELAY SET (ADS)
DELAB/DELCD output voltage ADS = CS = 0 V 0.45 0.5 0.55 V
ADS = 0 V,
CS = 2 V		 1.9 2 2.1
tDELAY Output delay(1)(3) ADS = CS = 0 V 450 560 620 ns
ADS bias current 0 V < ADS < 2.5 V,
0 V < CS < 2.5 V		 –20 20 µA
OUTPUT
VOH High-level output voltage (all outputs) IOUT = –10 mA, VDD to output 250 400 mV
VOL Low-level output voltage (all outputs) IOUT = 10 mA UCC1895 150 300 mV
UCC2895, UCC3895 150 250
tR Rise time(1) CLOAD = 100 pF 20 35 ns
tF Fall time(1) CLOAD = 100 pF 20 35 ns
PWM COMPARATOR
EAOUT to RAMP input offset voltage RAMP = 0 V,
DELAB = DELCD = REF		 0.72 0.85 1.05 V
Minimum phase shift(2)
(OUTA to OUTC, OUTB to OUTD)		 RAMP = 0 V,
EAOUT = 650 mV		 0.0% 0.85% 1.4%
tDELAY Delay(3)
(RAMP to OUTC, RAMP to OUTD)		 0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB = DELCD = REF		 70 120 ns
IR(bias) RAMP bias current RAMP < 5 V, CT = 2.2 V –5 5 µA
IR(sink) RAMP sink current RAMP = 5 V,
CT = 2.6 V		 UCC1895 10 19 mA
UCC2895, UCC3895 12 19
(1) Ensured by design. Not production tested.
(2) Minimum phase shift is defined as:
UCC1895 UCC2895 UCC3895 eq_note_slus157.gif

    where

  • tf(OUTA) = falling edge of OUTA signal
  • tf(OUTB) = falling edge of OUTB signal
  • tf(OUTC) = falling edge of OUTC signal
  • tf(OUTD) = falling edge of OUTD signal
  • tPERIOD = period of OUTA or OUTB signal

(3) Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: tf(OUTA) = falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2).
UCC1895 UCC2895 UCC3895 td1_b_d_slus157.gifFigure 1. Same Applies to OUTB and OUTD
UCC1895 UCC2895 UCC3895 td2_c_d_slus157.gifFigure 2. Same Applies to OUTC and OUTD