JAJSGJ8C November   2018  – September 2019 UCC20225-Q1 , UCC20225A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Thermal Derating Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 PWM Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in UCC20225-Q1 family
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing PWM Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Estimate Gate Driver Power Loss
        5. 10.2.2.5 Estimating Junction Temperature
        6. 10.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.6.1 Selecting a VCCI Capacitor
          2. 10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.6.3 Select a VDDB Capacitor
        7. 10.2.2.7 Dead Time Setting Guidelines
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 認定
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current DISABLE = VCCI 1.5 2.0 mA
IVDDA,
IVDDB 		VDDA and VDDB quiescent current DISABLE = VCCI 1.0 1.8 mA
IVCCI VCCI operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 mA
IVDDA,
IVDDB 		VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 mA
VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVCCI_ON Rising threshold VCCI_ON 2.55 2.7 2.85 V
VVCCI_OFF Falling threshold VCCI_OFF 2.35 2.5 2.65 V
VVCCI_HYS Threshold hysteresis 0.2 V
UCC20225A-Q1 VDD SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVDDA_ON,
VVDDB_ON 		Rising threshold VDDA_ON, VDDB_ON 5.7 6.0 6.3 V
VVDDA_OFF,
VVDDB_OFF 		Falling threshold VDDA_OFF, VDDB_OFF 5.4 5.7 6
VVDDA_HYS,
VVDDB_HYS 		Threshold hysteresis 0.3
UCC20225-Q1 VDD SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVDDA_ON,
VVDDB_ON 		Rising threshold VDDA_ON, VDDB_ON 8.3 8.7 9.2 V
VVDDA_OFF,
VVDDB_OFF 		Falling threshold VDDA_OFF, VDDB_OFF 7.8 8.2 8.7
VVDDA_HYS,
VVDDB_HYS 		Threshold hysteresis 0.5
PWM AND DISABLE
VPWMH, VDISH Input high voltage 1.6 1.8 2 V
VPWML, VDISL Input low voltage 0.8 1 1.2 V
VPWM_HYS, VDIS_HYS Input hysteresis 0.8 V
VPWM Negative transient, ref to GND, 50 ns pulse Not production tested, bench test only –5 V
OUTPUT
IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A
IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A
ROHA, ROHB Output resistance at high state IOUT = –10 mA, TA = 25°C, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Switching Characteristics and Output Stage for details. 5 Ω
ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω
VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 12 V, IOUT = –10 mA, TA = 25°C 11.95 V
VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25°C 5.5 mV
DEADTIME AND OVERLAP PROGRAMMING
Dead time Pull DT pin to VCCI 0 ns
DT pin is left open, min spec characterized only, tested for outliers 8 15 ns
RDT = 20 kΩ 160 200 240 ns