JAJSGJ8C November   2018  – September 2019 UCC20225-Q1 , UCC20225A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Thermal Derating Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 PWM Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in UCC20225-Q1 family
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing PWM Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Estimate Gate Driver Power Loss
        5. 10.2.2.5 Estimating Junction Temperature
        6. 10.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.6.1 Selecting a VCCI Capacitor
          2. 10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.6.3 Select a VDDB Capacitor
        7. 10.2.2.7 Dead Time Setting Guidelines
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 認定
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.12 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
UCC20225-Q1 UCC20225A-Q1 NO_LOAD_I_5_17.gif
Figure 4. Per Channel Current Consumption vs. Frequency (No Load, VDD = 12 V or 25 V)
UCC20225-Q1 UCC20225A-Q1 10nF_I_5_17.gif
Figure 6. Per Channel Current Consumption (IVDDA/B) vs. Frequency (10-nF Load, VDD = 12 V or 25 V)
UCC20225-Q1 UCC20225A-Q1 IQ_5_17.gif
Figure 8. Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature (No Load, Input Low, No Switching)
UCC20225-Q1 UCC20225A-Q1 RF_LOAD_NU.gif
A.
Figure 10. Rising and Falling Times vs. Load (VDD = 12 V)
UCC20225-Q1 UCC20225A-Q1 PD_T_NU.gif
Figure 12. Propagation Delay vs. Temperature
UCC20225-Q1 UCC20225A-Q1 PWD.gif
A.
Figure 14. Pulse Width Distortion vs. Temperature
UCC20225-Q1 UCC20225A-Q1 TDM_TEMP_NU.gif
Figure 16. Propagation Delay Matching (tDM) vs. Temperature
UCC20225-Q1 UCC20225A-Q1 D013_SLUSCO3.gif
Figure 18. UCC20225A-Q1 VDD 5-V UVLO Threshold vs. Temperature
UCC20225-Q1 UCC20225A-Q1 UVLO_VDD_TEMP_5_17.gif
Figure 20. UCC20225-Q1 VDD 8-V UVLO Threshold vs. Temperature
UCC20225-Q1 UCC20225A-Q1 INDIS_LO_5_17.gif
Figure 22. PWM/DIS Low Threshold
UCC20225-Q1 UCC20225A-Q1 DT_TEMP_NU.gif
Figure 24. Dead Time vs. Temperature (with RDT = 20 kΩ and 100 kΩ)
UCC20225-Q1 UCC20225A-Q1 1nF_I_5_17.gif
Figure 5. Per Channel Current Consumption (IVDDA/B) vs. Frequency (1-nF Load, VDD = 12 V or 25 V)
UCC20225-Q1 UCC20225A-Q1 IVDD_TEMP_5_17.gif
Figure 7. Per Channel (IVDDA/B) Supply Current Vs. Temperature (No Load, Different Switching Frequencies)
UCC20225-Q1 UCC20225A-Q1 Iq_IVCCI.gif
A.
Figure 9. IVCCI Quiescent Supply Current vs Temperature (No Load, DIS is High, No Switching)
UCC20225-Q1 UCC20225A-Q1 OUTR_5_17.gif
Figure 11. Output Resistance vs. Temperature
UCC20225-Q1 UCC20225A-Q1 PDVCC_NUNU.gif
Figure 13. Propagation Delay vs. VCCI
UCC20225-Q1 UCC20225A-Q1 TDM_VDD_NU.gif
Figure 15. Propagation Delay Matching (tDM) vs. VDD
UCC20225-Q1 UCC20225A-Q1 D017_SLUSCO3.gif
Figure 17. UCC20225A-Q1 VDD 5-V UVLO Hysteresis vs. Temperature
UCC20225-Q1 UCC20225A-Q1 VDD_HYS_5_17.gif
Figure 19. UCC20225-Q1 VDD 8-V UVLO Hysteresis vs. Temperature
UCC20225-Q1 UCC20225A-Q1 D001_SLUSCN0.gif
Figure 21. PWM/DIS Hysteresis vs. Temperature
UCC20225-Q1 UCC20225A-Q1 INDIS_HI_5_17.gif
Figure 23. PWM/DIS High Threshold
UCC20225-Q1 UCC20225A-Q1 DTM_TEMP_NU.gif
Figure 25. Dead Time Matching vs. Temperature (with RDT = 20 kΩ and 100 kΩ)