JAJSEU7B February   2018  – April 2024 UCC21222-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Minimum Pulses
    2. 6.2 Propagation Delay and Pulse Width Distortion
    3. 6.3 Rising and Falling Time
    4. 6.4 Input and Disable Response Time
    5. 6.5 Programmable Dead Time
    6. 6.6 Power-Up UVLO Delay to OUTPUT
    7. 6.7 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 7.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Designing INA/INB Input Filter
        3. 8.2.2.3 Select Dead Time Resistor and Capacitor
        4. 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Estimating Gate Driver Power Loss
        7. 8.2.2.7 Estimating Junction Temperature
        8. 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.8.1 Selecting a VCCI Capacitor
          2. 8.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.8.3 Select a VDDB Capacitor
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.11 Typical Characteristics

VDDA = VDDB= 15 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

UCC21222-Q1 Per Channel Current Consumption (IVDDA/B) vs Frequency (no load, VDD = 15V or 25V)
Figure 5-4 Per Channel Current Consumption (IVDDA/B) vs Frequency (no load, VDD = 15V or 25V)
UCC21222-Q1 Per Channel Current Consumption (IVDDA/B) vs Frequency (10-nF load, VDD = 15V or 25V)
Figure 5-6 Per Channel Current Consumption (IVDDA/B) vs Frequency (10-nF load, VDD = 15V or 25V)
UCC21222-Q1 Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature (no load, input low, no switching)
Figure 5-8 Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature (no load, input low, no switching)
UCC21222-Q1 Rising and Falling Times vs Load (VDD = 15V)
Figure 5-10 Rising and Falling Times vs Load (VDD = 15V)
UCC21222-Q1 Propagation Delay vs Temperature
Figure 5-12 Propagation Delay vs Temperature
UCC21222-Q1 Pulse Width Distortion vs Temperature
Figure 5-14 Pulse Width Distortion vs Temperature
UCC21222-Q1 Propagation Delay Matching (tDM) vs Temperature
Figure 5-16 Propagation Delay Matching (tDM) vs Temperature
UCC21222-Q1 VDD 8-V UVLO Hysteresis vs Temperature
Figure 5-18 VDD 8-V UVLO Hysteresis vs Temperature
UCC21222-Q1 IN/EN Low Threshold
Figure 5-20 IN/EN Low Threshold
UCC21222-Q1 Dead Time vs Temperature (with RDT = 20kΩ and 100kΩ)
Figure 5-22 Dead Time vs Temperature (with RDT = 20kΩ and 100kΩ)
UCC21222-Q1 Typical Output Waveforms
Figure 5-24 Typical Output Waveforms
UCC21222-Q1 Per Channel Current Consumption (IVDDA/B) vs Frequency (1-nF load, VDD = 15V or 25V)
Figure 5-5 Per Channel Current Consumption (IVDDA/B) vs Frequency (1-nF load, VDD = 15V or 25V)
UCC21222-Q1 Per Channel (IVDDA/B) Supply Current vs Temperature (no load, different switching frequencies)
Figure 5-7 Per Channel (IVDDA/B) Supply Current vs Temperature (no load, different switching frequencies)
UCC21222-Q1 IVCCI Quiescent Supply Current vs Temperature (no load, input low, no switching)
Figure 5-9 IVCCI Quiescent Supply Current vs Temperature (no load, input low, no switching)
UCC21222-Q1 Output Resistance vs Temperature
Figure 5-11 Output Resistance vs Temperature
UCC21222-Q1 Propagation Delay vs VCCI
Figure 5-13 Propagation Delay vs VCCI
UCC21222-Q1 Propagation Delay Matching (tDM) vs VDD
Figure 5-15 Propagation Delay Matching (tDM) vs VDD
UCC21222-Q1 VDD 8-V UVLO Threshold vs Temperature
Figure 5-17 VDD 8-V UVLO Threshold vs Temperature
UCC21222-Q1 IN/EN Hysteresis vs Temperature
Figure 5-19 IN/EN Hysteresis vs Temperature
UCC21222-Q1 IN/EN High Threshold
Figure 5-21 IN/EN High Threshold
UCC21222-Q1 Dead Time Matching vs Temperature (with RDT = 20kΩ and 100kΩ)
Figure 5-23 Dead Time Matching vs Temperature (with RDT = 20kΩ and 100kΩ)