JAJSEU7B February   2018  – April 2024 UCC21222-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Minimum Pulses
    2. 6.2 Propagation Delay and Pulse Width Distortion
    3. 6.3 Rising and Falling Time
    4. 6.4 Input and Disable Response Time
    5. 6.5 Programmable Dead Time
    6. 6.6 Power-Up UVLO Delay to OUTPUT
    7. 6.7 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
        2. 7.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Designing INA/INB Input Filter
        3. 8.2.2.3 Select Dead Time Resistor and Capacitor
        4. 8.2.2.4 Select External Bootstrap Diode and its Series Resistor
        5. 8.2.2.5 Gate Driver Output Resistor
        6. 8.2.2.6 Estimating Gate Driver Power Loss
        7. 8.2.2.7 Estimating Junction Temperature
        8. 8.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.8.1 Selecting a VCCI Capacitor
          2. 8.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.8.3 Select a VDDB Capacitor
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.9 Switching Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitance from VCCI to GND, VVDDx = 12V (for 5V and 8V UVLO) , 1-µF+100-nF capacitance from VDDA and VDDB to VSSA and VSSB, DT pin floating, EN = VCC or DIS = GND, TJ = –40°C to +150°C,  CL = 0 pF, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRISE Output Rise Time CL=1.8nF, VDDx=12V, 20% to 80% 8 ns
CL=1.8nF, VDDx=25V, 20% to 80% 8
tFALL Output Fall Time CL=1.8nF, VDDx=12V, 10% to 90% 8 ns
CL=1.8nF, VDDx=25V, 10% to 90% 8
tPDLH Propagation Delay – Low to High Input Pulse Width = 100ns, 500kHz, measure with Input VIH to output 10% 26 33 45 ns
tPDHL Propagation Delay – High to Low Input Pulse Width = 100ns, 500kHz, measure with Input VIL to output 90% 26 33 45 ns
tPD_DIS_HL DIS Response Delay – High to Low
tEN/DIS_FIL = 20 ns (typ), VDD=VDD_ON+0.2V and above,
Input Pulse Width = 100ns, 500kHz		 27 49 80 ns
tPD_DIS_LH DIS Response Delay – Low to High 27 49 80 ns
tPWmin Minimum Input Pulse Width That Passes to Output VDD=VDD_ON+0.2V and above 4 12 30 ns
tDM Propagation Delay Matching for Dual Channel Driver Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|		 0 6.5 ns
tDM Propagation Delay Matching for Dual Channel Driver Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|		 0 5 ns
tPWD Pulse Width Distortion Input Pulse Width = 100ns, 500kHz
|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB|		 0 5 ns
|CMH| High-level Common Mode Transient Immunity VCM = 1500V 125 V/ns
|CML| Low-level Common Mode Transient Immunity 125 V/ns