JAJSU92A April 2024 – June 2024 UCC21231
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When parasitic inductances are introduced by non-ideal PCB layout and long package leads, there could be ringing in the gate-source drive voltage of the power transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below the threshold. Below are a few examples of implementing negative gate drive bias.
Figure 8-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the isolated power supply output stage. The positive bias is set by the Zener diode voltage. If the isolated power supply, VA, is equal to 8 V, the turn-on voltage will be 5.1 V and turn-on voltage will be 8 V – 5.1 V ≈ 2.9 V. The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for a half-bridge configuration, and there will be steady state power consumption from RZ.
The circuit implementation in Figure 8-2 is suitable to drive GaN HEMT devices with regulated turn-on voltage for higher gate robustness. The negative voltage also protects the GaN from false turn-on during the miller charge due to low gate threshold voltage.
Figure 8-3 shows another example which uses two supplies (or single-input-double-output power supply). Power supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The configuration for channel B is the same as channel A. This solution requires more power supplies than the first example, however, it provides more flexibility when setting the positive and negative rail voltages.
The last example, shown in Figure 8-4, is a single power supply configuration and generates negative bias through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort among the three solutions. However, this solution has limitations: