SLUSF46A April 2024 – June 2024 UCC21231
PRODUCTION DATA
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A 2-layer pcb layout example is shown below. Components such as bypass capacitors are placed closely to the device pins.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.