JAJSCK9B september   2016  – december 2021 UCC21521

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programmable Dead Time
    5. 7.5 Powerup UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21521
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Gate to Source Resistor Selection
        5. 9.2.2.5 Estimate Gate Driver Power Loss
        6. 9.2.2.6 Estimating Junction Temperature
        7. 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.7.1 Selecting a VCCI Capacitor
          2. 9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.7.3 Select a VDDB Capacitor
        8. 9.2.2.8 Dead Time Setting Guidelines
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Powerup UVLO Delay to OUTPUT

Before the driver is ready to deliver a correct output state, there is a powerup delay from the UVLO rising edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40 μs) and tVDD+ to OUT for VDD UVLO (typically 50 μs). Consider the correct margin before launching the PWM signal after the driver's VCCI and VDD bias supplies are ready. Figure 7-5 and Figure 7-6 show the powerup UVLO delay timing diagram for VCCI and VDD.

If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output does not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1-μs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay helps to ensure safe operation during VCCI or VDD brownouts.

GUID-DDC6CE18-4897-4436-B113-2BCB98844DB9-low.gifFigure 7-5 VCCI Powerup UVLO Delay
GUID-9A613070-6AE3-46ED-B6DD-372EF5D13039-low.gifFigure 7-6 VDDA/B Powerup UVLO Delay