JAJSCK9B september   2016  – december 2021 UCC21521

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programmable Dead Time
    5. 7.5 Powerup UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21521
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Gate to Source Resistor Selection
        5. 9.2.2.5 Estimate Gate Driver Power Loss
        6. 9.2.2.6 Estimating Junction Temperature
        7. 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.7.1 Selecting a VCCI Capacitor
          2. 9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.7.3 Select a VDDB Capacitor
        8. 9.2.2.8 Dead Time Setting Guidelines
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15 V(1), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.5 2.0 mA
IVDDA,
IVDDB		 VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 1.8 mA
IVCCI VCCI per channel operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.0 mA
IVDDA,
IVDDB		 VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF, VDD=12 V 2.5 mA
(f = 500 kHz) current per channel, COUT = 100 pF, VDD=15 V 3.0 mA
VCCI UVLO THRESHOLDS
VVCCI_ON Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF Falling threshold VCCI_OFF 2.35 2.5 2.65 V
VVCCI_HYS Threshold hysteresis 0.2 V
UCC21521ADW VDD UVLO THRESHOLDS (5-V UVLO VERSION)
VVDDA_ON,
VVDDB_ON		 Rising threshold VDDA_ON, VDDB_ON 5.2 5.8 6.3 V
VVDDA_OFF,
VVDDB_OFF		 Falling threshold VDDA_OFF, VDDB_OFF 4.9 5.5 6 V
VVDDA_HYS,
VVDDB_HYS		 Threshold hysteresis 0.3 V
UCC21521DW VDD UVLO THRESHOLDS (8-V UVLO VERSION)
VVDDA_ON,
VVDDB_ON		 Rising threshold VDDA_ON, VDDB_ON 8 8.5 9 V
VVDDA_OFF,
VVDDB_OFF		 Falling threshold VDDA_OFF, VDDB_OFF 7.5 8 8.5 V
VVDDA_HYS,
VVDDB_HYS		 Threshold hysteresis 0.5 V
UCC21521CDW VDD UVLO THRESHOLDS (12-V UVLO VERSION)
VVDDA_ON,
VVDDB_ON		 Rising threshold VDDA_ON, VDDB_ON 12.5 13.5 14.5 V
VVDDA_OFF,
VVDDB_OFF		 Falling threshold VDDA_OFF, VDDB_OFF 11.5 12.5 13.5 V
VVDDA_HYS,
VVDDB_HYS		 Threshold hysteresis 1.0 V
INA and INB
VINAH, VINBH Input high voltage 1.6 1.8 2 V
VINAL, VINBL Input low voltage 0.8 1 1.2 V
VINA_HYS, VINB_HYS Input hysteresis 0.8 V
VINA, VINB Negative transient, ref to GND, 50 ns pulse Not production tested, bench test only –5 V
EN THRESHOLDS
VENH Enable high voltage 2.0 V
VENL Enable low voltage 0.8 V
OUTPUT
IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A
IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A
ROHA, ROHB Output resistance at high state IOUT = –10 mA, TA = 25°C, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Switching Characteristics and Output Stage for details. 5 Ω
ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω
VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 12 V, IOUT = –10 mA, TA = 25°C 11.95 V
VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25°C 5.5 mV
DEADTIME AND OVERLAP PROGRAMMING
Dead time Pull DT pin to VCCI Overlap determined by INA INB -
DT pin is left open, min spec characterized only, tested for outliers 0 8 15 ns
RDT = 20 kΩ 160 200 240 ns
(1) VDDA=VDDB=12 V is used for the test condition of 5-V and 8-V UVLO, and VDDA=VDDB = 15 V is used for 12-V UVLO.