SLUSDE1D November   2018  – February 2021 UCC21540 , UCC21540A , UCC21541 , UCC21542

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     UCC21540, UCC21541 Pin Functions
    2.     UCC21542 Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Minimum Pulses
    2. 8.2 Propagation Delay and Pulse Width Distortion
    3. 8.3 Rising and Falling Time
    4. 8.4 Input and Disable Response Time
    5. 8.5 Programmable Dead Time
    6. 8.6 Power-up UVLO Delay to OUTPUT
    7. 8.7 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC2154x
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 DT Pin Tied to VCCI
        2. 9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select Dead Time Resistor and Capacitor
        3. 10.2.2.3 Select External Bootstrap Diode and its Series Resistor
        4. 10.2.2.4 Gate Driver Output Resistor
        5. 10.2.2.5 Gate to Source Resistor Selection
        6. 10.2.2.6 Estimating Gate Driver Power Loss
        7. 10.2.2.7 Estimating Junction Temperature
        8. 10.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.8.1 Selecting a VCCI Capacitor
          2. 10.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.8.3 Select a VDDB Capacitor
        9. 10.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement Considerations
      2. 12.1.2 Grounding Considerations
      3. 12.1.3 High-Voltage Considerations
      4. 12.1.4 Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWK|14
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

11 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC2154x is between 3 V and 5.5 V. The output bias supply voltage (VDDA/VDDB) ranges from 6.0 V to 18 V. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. VDD and VCCI must not fall below their respective UVLO thresholds during normal operation. (For more information on UVLO see Section 9.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by the UCC2154x . The recommended maximum VDDA/VDDB is 18 V.

A local bypass capacitor should be placed between the VDD and VSS pins, to supply current when the output goes high into a capacitive load. This capacitor should be positioned as close to the device as possible to minimize parasitic impedance. A low ESR, ceramic surface mount capacitor is recommended. If the bypass capacitor impedance is too large, resistive and inductive parasitics could cause the supply voltage seen at the IC pins to dip below the UVLO threshold unexpectedly. To filter high frequency noise between VDD and VSS, it can be helpful to place a second capacitor with lower impedance at higher frequency. As an example, the primary bypass capacitor could be 1 µF, with a secondary high frequency bypass capacitor of 100 nF.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of the UCC2154x, this bypass capacitor has a minimum recommended value of 100 nF.