The UCC21738-Q1 features a PWM interlock for the IN+ and IN- pins, which can be used to prevent a phase leg shoot-through issue. As shown in Table 8-1, the output is logic low while both IN+ and IN- are logic high. When only IN+ is used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in the phase leg can be sent to the IN- pin. As shown in Figure 9-2, PWM_T is the PWM signal to the top-side switch, and PWM_B is the PWM signal to the bottom-side switch. For the top-side gate driver, the PWM_T signal is given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom-side gate driver, the PWM_B signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are high, the outputs of both gate drivers are logic low to prevent the shoot-through condition.

Figure 9-2 PWM Interlock for a Half Bridge