JAJSIW1A March   2020  – January 2024 UCC21739-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay
      1. 6.1.1 Regular Turn-OFF
    2. 6.2 Input Deglitch Filter
    3. 6.3 Active Miller Clamp
      1. 6.3.1 External Active Miller Clamp
    4. 6.4 Under Voltage Lockout (UVLO)
      1. 6.4.1 VCC UVLO
      2. 6.4.2 VDD UVLO
    5. 6.5 OC (Over Current) Protection
      1. 6.5.1 OC Protection with 2-Level Turn-OFF
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply
      2. 7.3.2  Driver Stage
      3. 7.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 7.3.4  Active Pulldown
      5. 7.3.5  Short Circuit Clamping
      6. 7.3.6  External Active Miller Clamp
      7. 7.3.7  Overcurrent and Short Circuit Protection
      8. 7.3.8  2-Level Turn-off
      9. 7.3.9  Fault ( FLT, Reset and Enable ( RST/EN)
      10. 7.3.10 Isolated Analog to PWM Signal Function
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input filters for IN+, IN- and RST/EN
        2. 8.2.2.2 PWM Interlock of IN+ and IN-
        3. 8.2.2.3 FLT, RDY and RST/EN Pin Circuitry
        4. 8.2.2.4 RST/EN Pin Control
        5. 8.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 8.2.2.6 External Active Miller Clamp
        7. 8.2.2.7 Overcurrent and Short Circuit Protection
          1. 8.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
          2. 8.2.2.7.2 Protection Based on Desaturation Circuit
          3. 8.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
        8. 8.2.2.8 Isolated Analog Signal Sensing
          1. 8.2.2.8.1 Isolated Temperature Sensing
          2. 8.2.2.8.2 Isolated DC Bus Voltage Sensing
        9. 8.2.2.9 Higher Output Current Using an External Current Buffer
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Driver Stage

UCC21739-Q1 has ±10A peak drive strength and is suitable for high power applications. The high drive strength can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage. UCC21739-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage. Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW state. The split output of the driver stage is depicted in Figure 7-1. The driver has rail-to-rail output by implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on resistance RNMOS is the same as ROL. The hybrid pull-up structure delivers the highest peak-source current when it is most needed, during the miller plateau region of the power semiconductor turn-on transient. The ROH in Figure 7-1 represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is much smaller than ROH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET, the pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3V below VDD voltage. The effective resistance of the hybrid pull-up structure during this period is about 2 x ROL . Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up impedance results in strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of the power semiconductor and reduces the turn on switching loss.

The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. This MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pull-down impedance not only results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering the miller effect.

GUID-A291F226-A088-4BAC-B3A3-CFA7F9644F58-low.gif Figure 7-1 Gate Driver Output Stage