JAJSHW8B
september 2019 – october 2020
UCC23313
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Function
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
電力定格
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
安全限界値
6.9
Electrical Characteristics
6.10
スイッチング特性
6.11
Insulation Characteristics Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Propagation Delay, rise time and fall time
7.2
IOH and IOL testing
7.3
CMTI Testing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Power Supply
8.3.2
Input Stage
8.3.3
Output Stage
8.3.4
Protection Features
8.3.4.1
Undervoltage Lockout (UVLO)
8.3.4.2
Active Pulldown
8.3.4.3
Short-Circuit Clamping
8.4
Device Functional Modes
8.4.1
ESD Structure
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Selecting the Input Resistor
9.2.2.2
Gate Driver Output Resistor
9.2.2.3
Estimate Gate-Driver Power Loss
9.2.2.4
Estimating Junction Temperature
9.2.2.5
Selecting VCC Capacitor
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
PCB Material
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DWY|6
サーマルパッド・メカニカル・データ
発注情報
jajshw8b_oa
8.2
Functional Block Diagram
Figure 8-1
Conceptual Block Diagram of a Isolated Gate Driver with an Opto Emulated Input Stage (SO6 pkg)
Figure 8-2
On-Off Keying (OOK) Based Modulation Scheme