JAJSU20A December   2023  – April 2024 UCC23525

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Thermal Derating Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Rise Time and Fall Time
    2. 6.2 IOH and IOL Testing
    3. 6.3 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 ESD Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Input Resistor
        2. 8.2.2.2 Gate Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VDD Capacitor
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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7.3.4.1 Undervoltage Lockout (UVLO)

UVLO function is implemented for VDD and VSS pins to prevent an under-driven condition on IGBTs and MOSFETs. When VDD is lower than UVLOR at device start-up or lower than UVLOF after start-up, the voltage-supply UVLO feature holds the effected output low, regardless of the input forward current as shown in Table 7-1. The VDD UVLO protection has a hysteresis feature (UVLOhys). This hysteresis prevents chatter when the power supply produces ground noise which allows the device to permit small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly.

When VDD drops below UVLOF, a delay, tUVLO_rec occurs on the output when the supply voltage rises above UVLOR again.

GUID-20231214-SS0I-D5MH-GDVL-DKRRXGXCR9LQ-low.svg Figure 7-5 UVLO functionality