JAJSU20A December   2023  – April 2024 UCC23525

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Thermal Derating Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Rise Time and Fall Time
    2. 6.2 IOH and IOL Testing
    3. 6.3 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 ESD Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Input Resistor
        2. 8.2.2.2 Gate Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VDD Capacitor
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWY|6
サーマルパッド・メカニカル・データ

5.9 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VDD–VSS= 15V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output-signal Rise Time CLoad = 1.8nF, VDD=15V, 20% to 80% 5 ns
tf Output-signal Fall Time CLoad = 1.8nF, VDD=15V, 90% to 10% 11 ns
tPLH Propagation Delay, Low to High CLoad = 1.8nF, VDD=15V, IF=10mA
FSW = 20 kHz, (50% Duty Cycle)
measure with Input IFLH to output 10%		 100 ns
tPHL Propagation Delay, High to Low CLoad = 1.8nF, VDD=15V, IF=10mA
FSW = 20 kHz, (50% Duty Cycle)
measure with Input IFLH to output 90%		 100 ns
tPWD Pulse Width Distortion |tPHL – tPLH| CLoad = 1.8nF, VDD=15V, IF=10mA
FSW = 20 kHz, (50% Duty Cycle)		 30 ns
tsk(pp) Part-to-Part Skew in Propagation Delay Between any Two Parts(1) CLoad = 1.8nF, VDD=15V, IF=10mA
FSW = 20 kHz, (50% Duty Cycle)		 25 ns
tUVLO_HI_OUT VDD UVLO HI Delay to OUT 10% HI IF=10mA 2 5 8 µs
tUVLO_LO_OUT VDD UVLO LO Delay to OUT 90% LO IF=10mA, VDD>6.2V 6 10 µs
CMTIH Common-mode Transient Immunity (Output High)(2) IF = 10 mA, VCM = 1000 V 200 V/ns
CMTIL Common-mode Transient Immunity (Output Low) (2) VF = 0 V, VCM = 1000 V 200 V/ns
tPWmin Minimum Input Pulse Width That Passes to Output CLoad = 1.8nF, VDD=15V, IF=10mA 9 12 43 ns
(1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization.
(2) For best CMTI performance, we recommend connecting single resistor to the Anode pin, and connecting Cathode pin directly to GND.