JAJSU20A December   2023  – April 2024 UCC23525

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Thermal Derating Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Rise Time and Fall Time
    2. 6.2 IOH and IOL Testing
    3. 6.3 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
        4. 7.3.4.4 ESD Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Input Resistor
        2. 8.2.2.2 Gate Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VDD Capacitor
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWY|6
サーマルパッド・メカニカル・データ

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
General
CLR External clearance (1) Shortest terminal-to-terminal distance through air >8.5 mm
CPG External Creepage (1) Shortest terminal-to-terminal distance across the package surface >8.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material Group According to IEC 60664-1 I
Overvoltage category Rated mains voltage ≤ 600 VRMS I-III
Rated mains voltage ≤ 1000 VRMS I-II
DIN EN IEC 60747-17 (VDE 0884-17) (2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 1063 VRMS
DC voltage 1500 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		 7071 VPK
VIMP Maximum inpulse voltage (3) Tested in air, 1.2/50-µs waveform per IEC 62368-1 7692 VPK
VIOSM Maximum surge isolation voltage (4) VIOSM ≥ 1.3 x VIMP ;Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-1 10000 VPK
qpd Apparent charge (5) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM , tm = 10 s		 ≤5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s		 ≤5
Method b1: At routine test (100% production) and preconditioning (type test):
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM , tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)		 ≤5
CIO Barrier capacitance, input to output (6) VIO = 0.4 × sin (2πft), f = 1 MHz 1 pF
RIO Insulation resistance, input to output (6) VIO = 500 V, TA = 25°C >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011
VIO = 500 V at TS = 150°C >109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Maximum withstanding isolation voltage VTEST = VISO, t = 60 s (qualification),
VTEST = 1.2 × VISO, t = 1 s (100% production)		 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
(2) UCC23525 is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-pin device.