JAJSFV5C July   2018  – March 2022 UCC24624

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Synchronous Rectifier Control
      3. 8.3.3 Turn-off Threshold Adjustment
      4. 8.3.4 Noise Immunity
        1. 8.3.4.1 On-Time Blanking
        2. 8.3.4.2 Off-Time Blanking
        3. 8.3.4.3 Two-Channel Interlock
        4. 8.3.4.4 SR Turn-on Re-arm
        5. 8.3.4.5 Adaptive Turn-on Delay
      5. 8.3.5 Gate Voltage Clamping
      6. 8.3.6 Standby Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Run Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MOSFET Selection
        2. 9.2.2.2 Snubber Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Snubber Design

It may be required to adjust snubbing components C3, C4, R2 and R5 to dampen noise.

To adjust these components requires knowing the LLC transformers secondary leakage inductance (Lslk) and measuring the secondary resonant ring frequency (fr) in circuit at minimal load of 10% or less. TI also recommends that the SR is not engaged while doing this and capacitors C3 and C4 are removed from the evaluation module. ConnectTP6 to ground to disable the gate driver.

The secondary winding capacitance (Cs) then needs to be calculated based on Equation 4. Note that for a transformer with a secondary winding leakage inductance of 3.8 µH and a ring frequency of 2 MHz, the parasitic capacitance would be 1.7 nF.

Equation 4. GUID-A631C599-B253-46AD-831B-DCDCF5F857AF-low.gif

Based on the calculated Cs, Lslk and fr the snubber resistors R2 and R5 can be set to critically dampen the ringing on the secondary, which requires setting the Q of the circuit equal to 1.

Equation 5. GUID-38B5F906-15DC-43EB-9F83-12F98975CC6F-low.gif

Capacitors C3 and C5 are used to limit the time the snubber resistor is applied to the aux winding during the switching cycle. It is recommended to set the snubber capacitor C3 with Equation 6 based on the LLC converters minimum switching frequency (fSW). For an LLC converter with a minimum switching at 85 kHz in the example would require a C3 and C4 would be roughly 497 pF.

Equation 6. GUID-F6E1949D-F280-4C0E-979F-66CFA5A01121-low.gif

Note that the calculations for R2, R5, C3, and C4 are just starting points and must be adjusted based on individual preference, performance and efficiency requirements.