JAJSNN2B October 2023 – July 2024 UCC25660
PRODUCTION DATA
Control of the output voltage is provided by a voltage regulator circuit located on the secondary side of the isolation barrier. The demand signal from the secondary-side regulator circuit is transferred across the isolation barrier using an optocoupler.
A constant current source IFB is generated from VCCP voltage and connected to FB pin. A resistor RFB is also connected to this current source with a PMOS in series. During normal operation, the PMOS is always on, so that the FB pin voltage is equal to the Zener diode reference voltage plus the voltage drop on the PMOS source to gate.
The control signal FBReplica is depicted using the equation below.
From this equation, when IOPTO increases, IRFB decreases, decreasing the FBReplica . In this way, the control signal is inverted. When IOPTO continues to increase and reaches the value of IFB, the FB pin voltage starts to drop because there is not enough current flow through the PMOS. FB pin pulled low impacts the system transient response, due to the extra delay introduced by charging the parasitic capacitor of the optocoupler to pull up the FB pin voltage. A FB pin voltage clamp circuit is used to prevent this scenario. When FB pin voltage drops below the FB pin clamp voltage threshold, an extra current source is turned on to clamp the FB voltage. The clamp strength is IFBClamp . The FB pin clamp circuit improves the system transient performance from light load to heavy load. The FB pin clamp operation is shown in the figure below.