JAJSNN2B October   2023  – July 2024 UCC25660

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brown in and Brown out Tresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Threshold Programming
        4. 7.5.3.4 PFC On/Off
      4. 7.5.4 X-Capacitor Discharge
        1. 7.5.4.1 Detecting Through HV Pin Only
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
        2. 8.4.2.2 Schematics
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

UCC25660 DDB Package16-Pin SOIC (Pins 2, 13 removed)Top View Figure 5-1 DDB Package16-Pin SOIC (Pins 2, 13 removed)Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
HV 1 I

High-voltage (HV) Startup and X-Capacitor Discharge.

This pin is used to to perform HV startup. After startup is completed, the HV pin is used for AC presence detection and X-Capacitor discharge. This pin is connected to the rectified AC line ( for UCC256601 and 604) or input bulk capacitor ( for UCC256602).
2 - Missing. HV spacer for creepage between high voltage and low voltage pins
BLK 3 I

Bulk input UVLO/OVLO and input voltage feedforward.

This pin is connected to a resistor divider that looks at bulk capacitor voltage.

OVP/OTP 4 I

Overvoltage protection and external overtemperature protection.

This pin connects through an NTC resistor to ground and to a Zener diode that connects to VCC
FB 5 I

Feedback signal.

This pin is connected to the collector of an opto-coupler. This pin is for feedback input.
LL 6 I

Light load operation options and burst mode threshold setting.

This pin is connected to an external resistor divider. The top resistor of the divider is connected to V5P. The impedance and voltage of this pin is used to select the theresholds for high frequncy and low frequency burst mode operation .
TSET 7 I/O

This pin is used to program the internal resonant tank current integrator (VCR synthesizer) time constant and minimum switching frequency. Depending on the option programmed, the maximum deadtime is also selected.

After the programming phase ends, TSET pin provides PFC on/off signal in the UCC256604 variant.
V5P 8 P

5V bias.

This pin is externally connected to a decoupling capacitor to GNDP.
ISNS 9 I

Resonant current sensing.

This pin senses the differentiated resonant capacitor voltage.This signal is internally used to:

1. Generate the control signal.

2. OCP & Cycle-by-Cycle current limiting.

3. Capacitive region avoidance.
GNDP 10 P This pin is connected to primary-side bulk capacitor negative terminal
LO 11 O Low-side gate driver output.
VCCP 12 P

IC supply voltage

This pin is connected to a decoupling capacitor. For applications including a bias winding on the LLC transformer, the VCC pin is connected through a diode to the bias winding. For applications where HV startup is disabled, VCCP is supplied by an auxilliary bias supply.

The VCCP pin is internally clamped to 19V.
13 N/A Missing pin. High-voltage spacer for creepage between high-voltage and low-voltage pins.
HB 14 P High-side gate driver bias. A capacitor connecting between HB and HS provides the high-side driver energy.
HO 15 O High-side gate driver output.
HS 16 P

High-side gate driver return. This pin is connected to the switch node of the half-bridge structure in the LLC power stage.

Please refere to section 8.2 Typical Application for more details.