JAJSNN2B October   2023  – July 2024 UCC25660

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brown in and Brown out Tresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Threshold Programming
        4. 7.5.3.4 PFC On/Off
      4. 7.5.4 X-Capacitor Discharge
        1. 7.5.4.1 Detecting Through HV Pin Only
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
        2. 8.4.2.2 Schematics
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

VCR Synthesizer

The UCC25660x ファミリ implements a VCR Synthesizer which integrates the resonant tank current to form a internal representation of the resonant capacitor voltage. By implementing the VCR synthesizer internally, the UCC25660x ファミリ provides for an ability to support very high frequency startup with controlled inrush currents and feed forward gain stage. The internal VCR synthesizer also makes the controller less succeptible to external noise picked up on the ISNS pin, making the controller more robust.

UCC25660 VCR Synthesizer Block
                    Diagram Figure 7-3 VCR Synthesizer Block Diagram

The first stage of the VCR synthesizer consists of a programable gain stage, used to implement the input voltage feed forward function. The second stage consist of a programable integrator with ramp compensation.

The UCC256604 has extended gain range enabled. This extended gain range helps to reduce the FBReplica variation when input voltage of the LLC changed over a wide range (3:1). This is achieved by reducing the gain of the programmable gain stage of the VCR synthesizer by turning on the Wide LLC EN bit.

To accommodate a wide frequency range of LLC power stages, the time constant of the integrator is externally configurable at startup to meet the needs of the design using the TSET pin. A voltage resistor divider between V5P and GNDP, connecting to TSET pin, configures the TSET settings. The UCC25660x ファミリ detected the divider ratio during startup. Based on the divider ratio, not only the time constant but the OCP threshold can be choosen. Once the time constant is chosen, the maximum dead-time is also configured. The column 2 in the tabled indicates the minimum frequency upto which the IPPC operation is maintained. Once the frequency falls below this, the controller can still maintian closed loop operation and works as a conventional current mode control.

In the table value TSET voltage values indicated are nominal values. Maximum and minimum range that can be used for each TSET setting is within +/- 48mV.

Table 7-1 TSET Programming Options table

TSET Option #

TSET Voltage

(V)

for 3.5V OCP

TSET Voltage

(V)

for 4V OCP

Minimum Frequency for IPPC Operation

(kHz)

Integrator Time Constant

(ns)

Maximum dead-time

(μs)

17 2.295 2.675 698.6 68 0.5
16 2.168 2.802 591.6 80 0.5
15 2.041 2.929 501 93 0.5
14 1.914 3.056 424.3 112 0.5
13 1.787 3.183 359.3 132 1
12 1.66 3.310 304.3 156 1
11 1.533 3.427 256.7 184 1
10 1.416 3.554 218.2 214 1
9 1.299 3.681 184.8 257 1
8 1.182 3.798 156.5 304 1
7 1.074 3.906 132.5 359 1
6 0.967 4.013 112.2 424 1
5 0.850 4.130 95 490 1
4 0.742 4.238 80.5 588 1
3 0.644 4.336 68.1 694 1
2 0.547 4.433 57.7 820 1
1 0.450 4.532 48.9 968 1
X <0.392 >4.589 X X X