JAJS224D
December 2006 – July 2024
UCC27200
,
UCC27201
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Timing Diagrams
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Input Stages
6.3.2
Undervoltage Lockout (UVLO)
6.3.3
Level Shift
6.3.4
Boot Diode
6.3.5
Output Stages
6.4
Device Functional Modes
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input Threshold Type
7.2.2.2
VDD Bias Supply Voltage
7.2.2.3
Peak Source and Sink Currents
7.2.2.4
Propagation Delay
7.2.2.5
Power Dissipation
7.2.3
Application Curves
8
Power Supply Recommendations
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
10
Device and Documentation Support
10.1
サード・パーティ製品に関する免責事項
10.2
Documentation Support
10.2.1
Related Documentation
10.3
ドキュメントの更新通知を受け取る方法
10.4
サポート・リソース
10.5
Trademarks
10.6
静電気放電に関する注意事項
10.7
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
DDA|8
MPDS092F
DRM|8
MPDS160B
サーマルパッド・メカニカル・データ
DDA|8
PPTD087E
DRM|8
QFND139B
発注情報
jajs224d_oa
jajs224d_pm
6
Detailed Description