JAJSC46C February   2011  – July 2024 UCC27200A , UCC27201A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages
      2. 6.3.2 UVLO (Undervoltage Lockout)
      3. 6.3.3 Level Shift
      4. 6.3.4 Boot Diode
      5. 6.3.5 Output Stages
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Threshold Type
        2. 7.2.2.2 VDD Bias Supply Voltage
        3. 7.2.2.3 Peak Source and Sink Currents
        4. 7.2.2.4 Propagation Delay
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

UCC27200A UCC27201A D Package8-Pin SOICTop ViewFigure 4-1 D Package8-Pin SOICTop View
UCC27200A UCC27201A DRM Package8-Pin VSONTop ViewFigure 4-3 DRM Package8-Pin VSONTop View
UCC27200A UCC27201A DPR Package10-Pin WSONTop ViewFigure 4-5 DPR Package10-Pin WSONTop View
UCC27200A UCC27201A DDA Package8-Pin SOIC With Exposed PowerPADTop ViewFigure 4-2 DDA Package8-Pin SOIC With Exposed PowerPADTop View
UCC27200A UCC27201A DRC Package9-Pin VSONTop ViewFigure 4-4 DRC Package9-Pin VSONTop View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME DRM/D/DDA DRC DPR
VDD 1 1 1 I Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22μF to 1.0μF.
HB 2 2 2 I High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022μF to 0.1μF, the value is dependant on the gate charge of the high-side MOSFET however.
HO 3 3 3 O High-side output. Connect to the gate of the high-side power MOSFET.
HS 4 4 4 I High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
HI 5 6 7 I High-side input.
LI 6 7 8 I Low-side input.
VSS 7 8 9 O Negative supply terminal for the device which is generally grounded.
LO 8 9 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
N/C — 5 5/6 — No connection. Pins labeled N/C have no connection.
PowerPAD(1) — — — — Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance.
(1) Pin VSS and the exposed thermal die pad are internally connected on the DRC package only. The thermal pad is not directly connected to any leads of the package on the DDA, DRM and DPR packages; however, it is electrically and thermally connected to the substrate which is the ground of the device.