JAJSGJ6B November   2018  – May 2022 UCC27282

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Input Stages and Interlock
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current VLI = VHI = 0 0.3 0.4 mA
IDDO VDD operating current f = 500 kHz, CLOAD = 0 2.2 4.5 mA
IHB HB quiescent current VLI = VHI = 0 V 0.2 0.4 mA
IHBO HB operating current f = 500 kHz, CLOAD = 0 2.5 4 mA
IHBS HB to VSS quiescent current VHS = VHB = 100 V 5.0 50 μA
IHBSO HB to VSS operating current(1) f = 500 kHz, CLOAD = 0 0.1 mA
IDD_DIS IDD when driver is disabled VEN = 0 7.0 μA
INPUT
VHIT Input rising threshold 1.9 2.1 2.4 V
VLIT Input falling threshold 0.9 1.1 1.3 V
VIHYS Input voltage Hysteresis 1.0 V
RIN Input pulldown resistance 100 250 350 kΩ
ENABLE
VEN Voltage threshold on EN pin to enable the driver 1.54 2.0 V
VDIS Voltage threshold on EN pin to disable the driver 0.7 1.21 V
VENHYS Enable pin Hysteresis 0.3 V
REN EN pin internal pull-down resistor 250 kΩ
TEN Time to enable the driver once the EN pin is pulled high VEN = 2V 18 μs
TDIS Time to disable the driver once the EN pin is pulled low VEN = 0V 1.5 μs
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
VDDR VDD rising threshold 4.7 5.0 5.4 V
VDDF VDD falling threshold 4.2 4.5 4.9 V
VDDHYS VDD threshold hysteresis 0.5 V
VHBR HB rising threshold with respect to HS pin 3.3 3.7 4.4 V
VHBF HB falling threshold with respect to HS pin 3.0 3.3 4.1 V
VHBHYS HB threshold hysteresis 0.3 V
BOOTSTRAP DIODE
VF Low-current forward voltage IVDD-HB = 100 μA 0.55 0.85 V
VFI High-current forward voltage IVDD-HB = 80 mA 0.88 1.0 V
RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 1.5 2.5 Ω
LO GATE DRIVER
VLOL Low level output voltage ILO = 100 mA 0.085 0.4 V
VLOH High level output voltage ILO = -100 mA, VLOH = VDD – VLO 0.13 0.42 V
Peak pullup current (1) VLO = 0 V 3.0 A
Peak pulldown current (1) VLO = 12 V 3.0 A
HO GATE DRIVER
VHOL Low level output voltage IHO = 100 mA 0.1 0.4 V
VHOH High level output voltage IHO = –100 mA, VHOH = VHB- VHO 0.13 0.42 V
Peak pullup current (1) VHO = 0 V 3.0 A
Peak pulldown current (1) VHO = 12 V 3.0 A
(1) Parameter not tested in production