JAJSGJ6B November   2018  – May 2022 UCC27282

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Input Stages and Interlock
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.3 Selecting External Gate Resistor

In high-frequency switching power supply applications where high-current gate drivers such as the UCC27282 are used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on the gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak output current capability. In such applications external gate resistors can limit the peak output current of the gate driver. it is recommended that there should be provision of external gate resistor whenever the layout or application permits.

Use Equation 9 to calculate the driver high-side pull-up current.

Equation 9. GUID-8CDB9D1D-F88A-4917-8642-7539F8FFE84F-low.gif

where

  • IOHH is the high-side, peak pull-up current
  • VDH is the bootstrap diode forward voltage drop
  • RHOH is the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be calculated from test conditions (RHOH = VHOH/IHO)
  • RGATE is the external gate resistance connected between driver output and power MOSFET gate
  • RGFET(int) is the MOSFET internal gate resistance provided by MOSFET datasheet

Use Equation 10 to calculate the driver high-side sink current.

Equation 10. GUID-CCF72706-64D7-4D52-B36D-46E7344D7BB2-low.gif

where

  • RHOL is the gate driver internal high-side pull-down resistance

Use Equation 11 to calculate the driver low-side source current.

Equation 11. GUID-27CA6CD2-3745-4365-AE81-0540FFC47494-low.gif

where

  • RLOH is the gate driver internal low-side pull-up resistance

Use Equation 12 to calculate the driver low-side sink current.

Equation 12. GUID-4F6A94FD-CF84-488C-8DF3-B99537A2DC15-low.gif

where

  • RLOL is the gate driver internal low-side pull-down resistance

Both high and low-side channels of the gate driver have a peak current rating of ±3 A. These equations help reduce the peak current if needed. To establish different rise time value compared to fall time value, external gate resistor can be anti-paralleled with diode-resistor combination as shown in Figure 8-1. Generally selecting an optimal value or configuration of external gate resistor is an iterative process. For additional information on selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers