To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be as fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the UCC27282 is designed with high drive current capability and low resistance of the output stages. One of the common way to test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of the outputs would provide idea of drive capability of the gate driver device. There must not be any resistance in this test circuit. Figure 8-3 and Figure 8-4 shows rise time and fall time of HO respectively of UCC27282. Figure 8-5 and Figure 8-6 shows rise time and fall time of LO respectively of UCC27282. For accuracy purpose, the VDD and HB pin of the gate driver device were connected together. HS and VSS pins are also connected together for this test.
Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This method is also useful in comparing performance of two or more gate driver devices.
As explained in Section 8.2.2.4, propagation delay plays an important role in reliable operation of many applications. Figure 8-7 and Figure 8-8
Figure 8-8 shows propagation delay and delay matching of UCC27282. In many switching power supply applications input signals to the gate driver have large amplitude high frequency noise. If there is no filter employed at the input, then there is a possibility of false signal passing through the gate driver and causing shoot-through on the output. UCC27282 prevents such shoot-through. If two inputs are high at the same time, UCC27282 shuts both the outputs off. Figure 8-9 shows interlock feature of UCC27282 and Figure 8-10 shows input negative voltage handling capability of UCC27282.
| VDD = VHB = 6 V, HS =
VSS |
CLOAD = 10
nF |
Ch4 = HO |
Figure 8-3 HO
Rise Time
A.
| VDD =
VHB = 6 V, HS = VSS |
CLOAD = 10
nF |
Ch4 = LO |
Figure 8-5 LO
Rise Time
A.
| VDD = 6 V |
CLOAD = 2
nF |
Ch1 = HI Ch2 = LI Ch3 = HO
Ch4 = LO |
Figure 8-7 Propagation Delay and Delay Matching
A.
| VDD =
VHB = 12 V, HS = VSS |
CLOAD = 0
nF |
|
Figure 8-9 Input
Shoot-through Protection or Interlock
| VDD = VHB=6 V, HS =
VSS |
CLOAD = 10
nF |
Ch4 = HO |
Figure 8-4 HO
Fall Time
A.
| VDD =
VHB = 6 V, HS = VSS |
CLOAD = 10
nF |
Ch4 = LO |
Figure 8-6 LO
Fall Time
A.
| VDD = 6 V |
CLOAD = 2
nF |
Ch1 = HI Ch2 = LI Ch3 = HO
Ch4 = LO |
Figure 8-8 Propagation Delay and Delay Matching
A.
| VDD =
10 V Vin = 100 V |
CL =
1 nF |
Ch1 = HI Ch2 =
LI Ch3 = HO Ch4 = LO |
Figure 8-10 Input
Negative Voltage