JAJSJ98B June   2020  – April 2022 UCC27288

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shifter
      4. 7.3.4 Output Stage
      5. 7.3.5 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 External Bootstrap Diode and Series Resistor
        3. 8.2.2.3 Estimate Driver Power Losses
        4. 8.2.2.4 Selecting External Gate Resistor
        5. 8.2.2.5 Delays and Pulse Width
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed wiring board (PWB) layout guidelines.

  • Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the external MOSFETs.
  • To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).
  • In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source of the high-side MOSFET and the source of the low-side MOSFET (synchronous rectifier) must be minimized.
  • Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling of switching noise into the ground plane is minimized.
  • Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the device. Generally it is connected to the ground plane which is the same as VSS of the device. It is recommended to connect this pad to the VSS pin only.
  • Grounding considerations:
    • The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the MOSFETs as possible.
    • The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.