JAJSJ98B June   2020  – April 2022 UCC27288

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shifter
      4. 7.3.4 Output Stage
      5. 7.3.5 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 External Bootstrap Diode and Series Resistor
        3. 8.2.2.3 Estimate Driver Power Losses
        4. 8.2.2.4 Selecting External Gate Resistor
        5. 8.2.2.5 Delays and Pulse Width
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +140°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PROPAGATION DELAYS
tDLFFVLI falling to VLO fallingSee Figure 6-11630ns
tDHFFVHI falling to VHO fallingSee Figure 6-11630ns
tDLRRVLI rising to VLO risingSee Figure 6-11630ns
tDHRRVHI rising to VHO risingSee Figure 6-11630ns
DELAY MATCHING
tMONFrom LO being ON to HO being OFFSee Figure 6-117ns
tMOFFFrom LO being OFF to HO being ONSee Figure 6-117ns
OUTPUT RISE AND FALL TIME
tRLO, HO rise timeCLOAD = 1800 pF, 10% to 90%12ns
tFLO, HO fall timeCLOAD = 1800 pF, 90% to 10%10ns
tRLO, HO (3 V to 9 V) rise timeCLOAD = 0.1 μF, 30% to 70%0.330.6μs
tFLO, HO (3 V to 9 V) fall timeCLOAD = 0.1 μF, 70% to 30%0.230.6μs
MISCELLANEOUS
TPW,minMinimum input pulse width that changes the output20ns
GUID-0A2BB0C7-3778-4D50-9C65-B955E1C00A50-low.gifFigure 6-1 Timing Diagram