JAJSRH6E February   2010  – November 2023 UCC27321-Q1 , UCC27322-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Source and Sink Capabilities During Miller Plateau
      4. 8.3.4 VDD
      5. 8.3.5 Drive Current and Power Requirements
      6. 8.3.6 Enable
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Configuration
        2. 9.2.2.2 Input Threshold Type
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Peak Source and Sink Currents
        5. 9.2.2.5 Enable and Disable Function
        6. 9.2.2.6 Propagation Delay
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1.     40
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
    4. 11.4 Power Dissipation
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-CE3BBF99-4298-44AF-9E83-725C5B30F9F0-low.svg Figure 6-1 D Package8-Pin SOICTop View
GUID-1EA0E10A-F0E2-45B3-9DF6-ACD5E7B44430-low.svg Figure 6-2 DGN Package8-Pin MSOP with PowerPADTop View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
AGND 4 GND The AGND and the PGND must be connected by a single thick trace directly under the device. There must be a low ESR, low ESL capacitor of 0.1 µF between VDD (pin 1) and AGND. The power MOSFETs must be placed on the PGND side of the device while the control circuit must be on the AGND side of the device. The control circuit ground must be common with the AGND while the PGND must be common with the source of the power FETs.
ENBL 3 I Enable input for the driver with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with a pullup resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state.
IN 2 I Input signal of the driver, which has logic-compatible threshold and hysteresis. For UCC27321-Q1, IN is inverting, and for UCC37322-Q1, IN is noninverting.
OUT 6, 7 O Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak drive current to the gate of a power MOSFET.
PGND 5 GND Common ground for output stage. This ground must be connected very close to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing effects due to output switching di/dt, which can affect the input threshold. There must be a low ESR, low ESL capacitor of 0.1 µF between VDD (pin 8) and PGND.
VDD 1, 8 PWR Supply voltage and the power input connections for this device. These pins must be connected together externally.
PowerPAD Pad GND PowerPAD on DGN package only. The PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device.